摘要:
In a fee calculating apparatus for calculating a delivery fee, when weight data obtained by measurement in a weight measuring section such as an electronic scale, length data obtained by measurement in a length measuring section such as an automatic measure, and area data input by area data input means are all supplied to the calculating means, a delivery fee is calculated from the data by the calculating means in accordance with fee tables such as a parcel rank conversion table and a fee conversion table.
摘要:
A time data processing apparatus comprises a time-keeping memory for storing time data, a time-keeping circuit for renewing the time data read out from the time-keeping memory and writing the renewed time data into the time-keeping memory, repeatedly at predetermined regular intervals, and a central processing unit being accessible to the time data in the time-keeping memory while the time-keeping circuit does not make the time-keeping memory accessed.
摘要:
A data reader has a data reading means for reading data from a recording medium and producing an analog signal. The data reader also has a switching circuit having one terminal connected to the output terminal of the reading means. When the potential difference across the two terminals of the switching circuit falls within a predetermined range, the switching element is turned off. The switching element is turned on when the potential difference falls outside the predetermined range. The reader further has a hold circuit connected to the switching circuit and for holding a potential applied thereto. The reader also has a comparator which compares the analog signal from the data reading means with the potential held by the hold circuit and which produces a digital signal.
摘要:
An electronic timepiece circuit is provided with an oscillator for producing a reference signal and a frequency dividing circuit which frequency-divides the reference signal from the oscillator to produce a signal with given time intervals. Clock data stored in the memory is read out therefrom by a timing signal corresponding to the output signal from a given stage of the frequency dividing circuit and is loaded into a shift register where it is stored temporarily. The clock data stored in the memory is read out therefrom at given time intervals by a control signal obtained in accordance with the output signal from a given stage of the frequency dividing circuit, and the read out clock data, together with the clock data read out to the shift register, is subjected to a given operation, with the result that the clock data is updated. The updated clock signal is loaded into the memory by a control circuit.