公开(公告)号：US08324698B2

公开(公告)日：2012-12-04

申请号：US12930333

申请日：2011-01-04

申请人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

发明人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

IPC分类号： H01L29/82

CPC分类号： H01L27/228 ,  H01L43/12

摘要： A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.

公开(公告)号：US20110101478A1

公开(公告)日：2011-05-05

申请号：US12930333

申请日：2011-01-04

申请人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

发明人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

IPC分类号： H01L29/82

CPC分类号： H01L27/228 ,  H01L43/12

摘要： A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.

公开(公告)号：US08183061B2

公开(公告)日：2012-05-22

申请号：US12931648

申请日：2011-02-07

申请人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

发明人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

IPC分类号： H01L21/441

CPC分类号： H01L27/228 ,  H01L43/12

摘要： A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.

摘要翻译： 公开了一种STT-MRAM集成方案，其中通过在CMOS着陆焊盘，接触和覆盖VAC的金属（VAM）焊盘上形成中间通孔接触（VAC）来简化MTJ和CMOS金属之间的连接，以及MTJ 在VAM上。 执行双镶嵌工艺，通过设备区域中的VAC / VAM / MTJ堆叠将BIT线金属连接到CMOS着陆焊盘，并通过设备区域外的BIT连接通孔将BIT线连接焊盘连接到CMOS连接焊盘。 VAM焊盘是由Ta，TaN或用作扩散阻挡层的其它导体制成的单层或复合材料，具有用于MTJ形成的高度光滑的表面，并且在化学机械抛光工艺期间提供了与补充介电材料的优异选择性。 每个VAC为500至3000埃厚，以最小化额外的电路电阻并最小化蚀刻负担。

公开(公告)号：US20110129946A1

公开(公告)日：2011-06-02

申请号：US12931648

申请日：2011-02-07

申请人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

发明人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

IPC分类号： H01L21/00

CPC分类号： H01L27/228 ,  H01L43/12

摘要： A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.

公开(公告)号：US07884433B2

公开(公告)日：2011-02-08

申请号：US12290495

申请日：2008-10-31

申请人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

发明人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

IPC分类号： H01L29/82

CPC分类号： H01L27/228 ,  H01L43/12

摘要： A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.

摘要翻译： 公开了一种STT-MRAM集成方案，其中通过在CMOS着陆焊盘，接触和覆盖VAC的金属（VAM）焊盘上形成中间通孔接触（VAC）来简化MTJ和CMOS金属之间的连接，以及MTJ 在VAM上。 执行双镶嵌工艺，通过设备区域中的VAC / VAM / MTJ堆叠将BIT线金属连接到CMOS着陆焊盘，并通过设备区域外的BIT连接通孔将BIT线连接焊盘连接到CMOS连接焊盘。 VAM焊盘是由Ta，TaN或用作扩散阻挡层的其它导体制成的单层或复合材料，具有用于MTJ形成的高度光滑的表面，并且在化学机械抛光工艺期间提供了与补充介电材料的优异选择性。 每个VAC为500至3000埃厚，以最小化额外的电路电阻并最小化蚀刻负担。

公开(公告)号：US20100109106A1

公开(公告)日：2010-05-06

申请号：US12290495

申请日：2008-10-31

申请人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

发明人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

IPC分类号： H01L29/82 ,  H01L21/00

CPC分类号： H01L27/228 ,  H01L43/12

摘要： A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.

摘要翻译： 公开了一种STT-MRAM集成方案，其中通过在CMOS着陆焊盘，接触和覆盖VAC的金属（VAM）焊盘上形成中间通孔接触（VAC）来简化MTJ和CMOS金属之间的连接，以及MTJ 在VAM上。 执行双镶嵌工艺，通过设备区域中的VAC / VAM / MTJ堆叠将BIT线金属连接到CMOS着陆焊盘，并通过设备区域外的BIT连接通孔将BIT线连接焊盘连接到CMOS连接焊盘。 VAM焊盘是由Ta，TaN或用作扩散阻挡层的其它导体制成的单层或复合材料，具有用于MTJ形成的高度光滑的表面，并且在化学机械抛光工艺期间提供了与补充介电材料的优异选择性。 每个VAC为500至3000埃厚，以最小化额外的电路电阻并最小化蚀刻负担。

公开(公告)号：US07919407B1

公开(公告)日：2011-04-05

申请号：US12590945

申请日：2009-11-17

申请人： Tom Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu ,  Adam Zhong ,  Chyu-Jiuh Torng

发明人： Tom Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu ,  Adam Zhong ,  Chyu-Jiuh Torng

IPC分类号： H01L21/4763

CPC分类号： H01L21/76807 ,  H01L21/76816 ,  H01L27/228

摘要： Described herein are novel, cost effective and scalable methods for integrating a CMOS level with a memory cell level to form a field induced MRAM device. The memory portion of the device includes N parallel word lines, which may be clad, overlaid by M parallel bit lines orthogonal to the word lines and individual patterned memory cells formed on previously patterned electrodes at the N×M intersections of the two sets of lines. The memory portion is integrated with a CMOS level and the connection between levels is facilitated by the formation of interconnecting vias between the N×M electrodes and corresponding pads in the CMOS level and by word line connection pads in the memory device level and corresponding metal pads in the CMOS level. Of particular importance are process steps that replace single damascene formations by dual damascene formations, different process steps for the formation of clad and unclad word lines and the formation of patterned electrodes for the memory cells prior to the patterning of the cells themselves.

摘要翻译： 这里描述了用于将CMOS电平与存储器单元级集成以形成场感应MRAM器件的新颖的，成本有效的和可扩展的方法。 器件的存储器部分包括N个并行字线，其可以由两条垂直于字线的M个并行位线和在两组线的N×M个交点处形成在先前图案化电极上的各个图案化存储单元重叠 。 存储器部分与CMOS电平集成，并且通过在CMOS电平中的N×M电极和相应焊盘之间的互连通孔以及存储器件级中的字线连接焊盘和对应的金属焊盘 在CMOS级别。 特别重要的是通过双镶嵌结构取代单个镶嵌地层的工艺步骤，用于形成包层和未包层字线的不同工艺步骤以及在细胞本身的图案化之前形成记忆单元的图案化电极。