公开(公告)号：US07919407B1

公开(公告)日：2011-04-05

申请号：US12590945

申请日：2009-11-17

申请人： Tom Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu ,  Adam Zhong ,  Chyu-Jiuh Torng

发明人： Tom Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu ,  Adam Zhong ,  Chyu-Jiuh Torng

IPC分类号： H01L21/4763

CPC分类号： H01L21/76807 ,  H01L21/76816 ,  H01L27/228

摘要： Described herein are novel, cost effective and scalable methods for integrating a CMOS level with a memory cell level to form a field induced MRAM device. The memory portion of the device includes N parallel word lines, which may be clad, overlaid by M parallel bit lines orthogonal to the word lines and individual patterned memory cells formed on previously patterned electrodes at the N×M intersections of the two sets of lines. The memory portion is integrated with a CMOS level and the connection between levels is facilitated by the formation of interconnecting vias between the N×M electrodes and corresponding pads in the CMOS level and by word line connection pads in the memory device level and corresponding metal pads in the CMOS level. Of particular importance are process steps that replace single damascene formations by dual damascene formations, different process steps for the formation of clad and unclad word lines and the formation of patterned electrodes for the memory cells prior to the patterning of the cells themselves.

摘要翻译： 这里描述了用于将CMOS电平与存储器单元级集成以形成场感应MRAM器件的新颖的，成本有效的和可扩展的方法。 器件的存储器部分包括N个并行字线，其可以由两条垂直于字线的M个并行位线和在两组线的N×M个交点处形成在先前图案化电极上的各个图案化存储单元重叠 。 存储器部分与CMOS电平集成，并且通过在CMOS电平中的N×M电极和相应焊盘之间的互连通孔以及存储器件级中的字线连接焊盘和对应的金属焊盘 在CMOS级别。 特别重要的是通过双镶嵌结构取代单个镶嵌地层的工艺步骤，用于形成包层和未包层字线的不同工艺步骤以及在细胞本身的图案化之前形成记忆单元的图案化电极。

公开(公告)号：US08324698B2

公开(公告)日：2012-12-04

申请号：US12930333

申请日：2011-01-04

申请人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

发明人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

IPC分类号： H01L29/82

CPC分类号： H01L27/228 ,  H01L43/12

摘要： A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.

公开(公告)号：US20110101478A1

公开(公告)日：2011-05-05

申请号：US12930333

申请日：2011-01-04

申请人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

发明人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

IPC分类号： H01L29/82

CPC分类号： H01L27/228 ,  H01L43/12

摘要： A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.

公开(公告)号：US07884433B2

公开(公告)日：2011-02-08

申请号：US12290495

申请日：2008-10-31

申请人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

发明人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

IPC分类号： H01L29/82

CPC分类号： H01L27/228 ,  H01L43/12

摘要： A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.

摘要翻译： 公开了一种STT-MRAM集成方案，其中通过在CMOS着陆焊盘，接触和覆盖VAC的金属（VAM）焊盘上形成中间通孔接触（VAC）来简化MTJ和CMOS金属之间的连接，以及MTJ 在VAM上。 执行双镶嵌工艺，通过设备区域中的VAC / VAM / MTJ堆叠将BIT线金属连接到CMOS着陆焊盘，并通过设备区域外的BIT连接通孔将BIT线连接焊盘连接到CMOS连接焊盘。 VAM焊盘是由Ta，TaN或用作扩散阻挡层的其它导体制成的单层或复合材料，具有用于MTJ形成的高度光滑的表面，并且在化学机械抛光工艺期间提供了与补充介电材料的优异选择性。 每个VAC为500至3000埃厚，以最小化额外的电路电阻并最小化蚀刻负担。

公开(公告)号：US20100109106A1

公开(公告)日：2010-05-06

申请号：US12290495

申请日：2008-10-31

申请人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

发明人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

IPC分类号： H01L29/82 ,  H01L21/00

CPC分类号： H01L27/228 ,  H01L43/12

摘要： A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.

摘要翻译： 公开了一种STT-MRAM集成方案，其中通过在CMOS着陆焊盘，接触和覆盖VAC的金属（VAM）焊盘上形成中间通孔接触（VAC）来简化MTJ和CMOS金属之间的连接，以及MTJ 在VAM上。 执行双镶嵌工艺，通过设备区域中的VAC / VAM / MTJ堆叠将BIT线金属连接到CMOS着陆焊盘，并通过设备区域外的BIT连接通孔将BIT线连接焊盘连接到CMOS连接焊盘。 VAM焊盘是由Ta，TaN或用作扩散阻挡层的其它导体制成的单层或复合材料，具有用于MTJ形成的高度光滑的表面，并且在化学机械抛光工艺期间提供了与补充介电材料的优异选择性。 每个VAC为500至3000埃厚，以最小化额外的电路电阻并最小化蚀刻负担。

公开(公告)号：US08183061B2

公开(公告)日：2012-05-22

申请号：US12931648

申请日：2011-02-07

申请人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

发明人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

IPC分类号： H01L21/441

CPC分类号： H01L27/228 ,  H01L43/12

摘要： A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.

摘要翻译： 公开了一种STT-MRAM集成方案，其中通过在CMOS着陆焊盘，接触和覆盖VAC的金属（VAM）焊盘上形成中间通孔接触（VAC）来简化MTJ和CMOS金属之间的连接，以及MTJ 在VAM上。 执行双镶嵌工艺，通过设备区域中的VAC / VAM / MTJ堆叠将BIT线金属连接到CMOS着陆焊盘，并通过设备区域外的BIT连接通孔将BIT线连接焊盘连接到CMOS连接焊盘。 VAM焊盘是由Ta，TaN或用作扩散阻挡层的其它导体制成的单层或复合材料，具有用于MTJ形成的高度光滑的表面，并且在化学机械抛光工艺期间提供了与补充介电材料的优异选择性。 每个VAC为500至3000埃厚，以最小化额外的电路电阻并最小化蚀刻负担。

公开(公告)号：US20110129946A1

公开(公告)日：2011-06-02

申请号：US12931648

申请日：2011-02-07

申请人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

发明人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

IPC分类号： H01L21/00

CPC分类号： H01L27/228 ,  H01L43/12

摘要： A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.

公开(公告)号：US09343463B2

公开(公告)日：2016-05-17

申请号：US12586900

申请日：2009-09-29

申请人： Tom Zhong ,  Adam Zhong ,  Wai-Ming J. Kan ,  Chyu-Jiuh Torng

发明人： Tom Zhong ,  Adam Zhong ,  Wai-Ming J. Kan ,  Chyu-Jiuh Torng

IPC分类号： H01L29/66 ,  H01L21/4763 ,  H01L27/105 ,  H01L21/768 ,  H01L23/522 ,  H01L27/22

CPC分类号： H01L27/105 ,  H01L21/76819 ,  H01L21/7684 ,  H01L23/522 ,  H01L27/228 ,  H01L2924/0002 ,  H01L2924/00

摘要： The structure and method of formation of an integrated CMOS level and active device level that can be a memory device level. The integration includes the formation of a “super-flat” interface between the two levels formed by the patterning of a full complement of active and dummy interconnecting vias using two separate patterning and etch processes. The active vias connect memory devices in the upper device level to connecting pads in the lower CMOS level. The dummy vias may extend up to an etch stop layer formed over the CMOS layer or may be stopped at an intermediate etch stop layer formed within the device level. The dummy vias thereby contact memory devices but do not connect them to active elements in the CMOS level.

摘要翻译： 集成CMOS级别和有源器件级别的结构和方法可以是存储器件级。 整合包括通过使用两个单独的图案化和蚀刻工艺对完整的有源和虚拟互连通孔进行图案化形成的两层之间形成“超平面”界面。 有源通孔将上部器件电平的存储器件连接到较低CMOS电平的连接焊盘。 虚拟通孔可以延伸到在CMOS层上形成的蚀刻停止层，或者可以在形成在器件级内的中间蚀刻停止层处停止。 因此，虚拟通孔接触存储器件，但不将它们连接到CMOS电平中的有源元件。

公开(公告)号：US08105948B2

公开(公告)日：2012-01-31

申请号：US12070286

申请日：2008-02-14

申请人： Adam Zhong ,  Wai-Ming Kan ,  Tom Zhong ,  Chyu-Jiuh Torng

发明人： Adam Zhong ,  Wai-Ming Kan ,  Tom Zhong ,  Chyu-Jiuh Torng

IPC分类号： H01L21/302

CPC分类号： H01L21/31053 ,  H01L43/12

摘要： A process is described for making contact to the buried capping layers of GMR and MTJ devices without the need to form and fill via holes. CMP is applied to the structure in three steps: (1) conventional CMP (2) a Highly Selective Slurry (HSS) is substituted for the conventional slurry to just expose the capping layer, and (3) the HSS is diluted and used to clean the surface as well as to cause a slight protrusion of the capping layers above the surrounding dielectric surface, making it easier the contact them without damaging the devices below.

摘要翻译： 描述了与GMR和MTJ装置的掩埋覆盖层接触而不需要形成和填充通孔的方法。 CMP结构分为三个步骤：（1）常规CMP（2）采用高选择性浆料（HSS）代替传统的浆料，仅暴露顶盖层，（3）将HSS稀释并用于清洗 表面以及使覆盖层在周围的电介质表面上稍微突出，使得更容易接触它们而不损坏下面的器件。

公开(公告)号：US20080225576A1

公开(公告)日：2008-09-18

申请号：US11724435

申请日：2007-03-15

申请人： Tom Zhong ,  Terry Kin Ting Ko ,  Chyu-Jiuh Torng ,  Wai-Ming Kan ,  Adam Zhong

发明人： Tom Zhong ,  Terry Kin Ting Ko ,  Chyu-Jiuh Torng ,  Wai-Ming Kan ,  Adam Zhong

IPC分类号： G11C11/00

CPC分类号： H01L27/222 ,  H01L43/12 ,  Y10S977/935

摘要： An MTJ pattern layout for a memory device is disclosed that includes two CMP assist features outside active MTJ device blocks. A first plurality of dummy MTJ devices is located in two dummy bands formed around an active MTJ device block. The inner dummy band is separated from the outer dummy band by the MTJ ILD layer and has a MTJ device density essentially the same as the MTJ device block. The outer dummy band has a MTJ device density at least 10% greater than the inner dummy band. The inner dummy band serves to minimize CMP edge effect in the MTJ device block while the outer dummy band improves planarization. A second plurality of dummy MTJ devices is employed in contact pads outside the outer dummy band and is formed between a WL ILD layer and a BIT ILD layer thereby minimizing delamination of the MTJ ILD layer.

摘要翻译： 公开了一种用于存储器件的MTJ图案布局，其包括主动MTJ器件块之外的两个CMP辅助特征。 第一组多个虚拟MTJ设备位于形成在活动MTJ设备块周围的两个虚拟带中。 内部虚拟带通过MTJ ILD层与外部虚拟带分离，并且具有与MTJ器件块基本相同的MTJ器件密度。 外虚拟带具有比内虚拟带大至少10％的MTJ装置密度。 内部虚拟带用于最小化MTJ器件块中的CMP边缘效应，而外部虚拟带改善了平坦化。 在外虚拟带外部的接触焊盘中采用第二多个虚拟MTJ器件，并且形成在WL ILD层和BIT ILD层之间，从而最小化MTJ ILD层的分层。