公开(公告)号：US08324698B2

公开(公告)日：2012-12-04

申请号：US12930333

申请日：2011-01-04

申请人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

发明人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

IPC分类号： H01L29/82

CPC分类号： H01L27/228 ,  H01L43/12

摘要： A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.

公开(公告)号：US20110101478A1

公开(公告)日：2011-05-05

申请号：US12930333

申请日：2011-01-04

申请人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

发明人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

IPC分类号： H01L29/82

CPC分类号： H01L27/228 ,  H01L43/12

摘要： A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.

公开(公告)号：US08183061B2

公开(公告)日：2012-05-22

申请号：US12931648

申请日：2011-02-07

申请人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

发明人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

IPC分类号： H01L21/441

CPC分类号： H01L27/228 ,  H01L43/12

摘要： A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.

摘要翻译： 公开了一种STT-MRAM集成方案，其中通过在CMOS着陆焊盘，接触和覆盖VAC的金属（VAM）焊盘上形成中间通孔接触（VAC）来简化MTJ和CMOS金属之间的连接，以及MTJ 在VAM上。 执行双镶嵌工艺，通过设备区域中的VAC / VAM / MTJ堆叠将BIT线金属连接到CMOS着陆焊盘，并通过设备区域外的BIT连接通孔将BIT线连接焊盘连接到CMOS连接焊盘。 VAM焊盘是由Ta，TaN或用作扩散阻挡层的其它导体制成的单层或复合材料，具有用于MTJ形成的高度光滑的表面，并且在化学机械抛光工艺期间提供了与补充介电材料的优异选择性。 每个VAC为500至3000埃厚，以最小化额外的电路电阻并最小化蚀刻负担。

公开(公告)号：US08133745B2

公开(公告)日：2012-03-13

申请号：US11975045

申请日：2007-10-17

申请人： Tom Zhong ,  Rongfu Xiao ,  Chyu-Jiuh Torng ,  Adam Zhong

发明人： Tom Zhong ,  Rongfu Xiao ,  Chyu-Jiuh Torng ,  Adam Zhong

IPC分类号： H01L21/00

CPC分类号： H01L43/12 ,  B82Y10/00 ,  H01L27/228

摘要： A method for forming a MTJ in a STT-MRAM is disclosed in which the easy-axis CD is determined independently of the hard-axis CD. One approach involves two photolithography steps and two etch steps to form a post in a hard mask which is transferred through a MTJ stack of layers by a third etch process. Optionally, the third etch may stop on the tunnel barrier or in the free layer. A second embodiment involves forming a first parallel line pattern on a hard mask layer and transferring the line pattern through the MTJ stack with a first etch step. A planar insulation layer is formed adjacent to the sidewalls in the line pattern and then a second parallel line pattern is formed which is transferred by a second etch through the MTJ stack to form a post pattern. Etch end point may be controlled independently for hard-axis and easy-axis dimensions.

摘要翻译： 公开了一种用于在STT-MRAM中形成MTJ的方法，其中容易轴CD独立于硬轴CD来确定。 一种方法涉及两个光刻步骤和两个蚀刻步骤，以在通过第三蚀刻工艺通过MTJ叠层堆叠的硬掩模中形成柱。 可选地，第三蚀刻可以在隧道势垒上或在自由层中停止。 第二实施例涉及在硬掩模层上形成第一平行线图案，并通过第一蚀刻步骤通过MTJ堆叠传送线图案。 平面绝缘层与线图案中的侧壁相邻地形成，然后形成第二平行线图案，其通过第二次蚀刻通过MTJ叠层转印以形成柱形图案。 蚀刻终点可以独立控制硬轴和易轴尺寸。

公开(公告)号：US20110129946A1

公开(公告)日：2011-06-02

申请号：US12931648

申请日：2011-02-07

申请人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

发明人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

IPC分类号： H01L21/00

CPC分类号： H01L27/228 ,  H01L43/12

摘要： A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.

公开(公告)号：US20090078927A1

公开(公告)日：2009-03-26

申请号：US11901999

申请日：2007-09-20

申请人： Rongfu Xiao ,  Chyu-Jiuh Torng ,  Tom Zhong ,  Witold Kula ,  Adam Zhong

发明人： Rongfu Xiao ,  Chyu-Jiuh Torng ,  Tom Zhong ,  Witold Kula ,  Adam Zhong

IPC分类号： H01L29/06 ,  H01L21/02

CPC分类号： H01L43/12 ,  Y10T428/24736

摘要： A composite hard mask is disclosed that enables sub-100 nm sized MTJ cells to be formed for advanced devices such as spin torque MRAMs. The hard mask has a lower non-magnetic metallic layer such as Ru to magnetically isolate an overlying middle metallic spacer such as MnPt from an underlying free layer. The middle metallic spacer provides a height margin during subsequent processing to avoid shorting between a bit line and the MTJ cell in the final device. An upper conductive layer may be made of Ta and is thin enough to allow a MTJ pattern in a thin overlying photoresist layer to be transferred through the Ta during a fluorocarbon etch without consuming all of the photoresist. The MTJ pattern is transferred through the remaining hard mask layers and underlying MTJ stack of layers with a second etch step using a C, H, and O etch gas composition.

摘要翻译： 公开了一种复合硬掩模，其能够为高级装置（例如自旋扭矩MRAM）形成次100nm大小的MTJ电池。 硬掩模具有较低的非磁性金属层，例如Ru，以将下层的中间金属间隔物（例如MnPt）与下层的自由层磁隔离。 中间金属间隔件在后续处理期间提供高度余量以避免位线和最终装置中的MTJ单元之间的短路。 上导电层可以由Ta制成，并且足够薄以使氟薄膜蚀刻中的薄覆盖光致抗蚀剂层中的MTJ图案能够通过Ta Ta传输而不消耗所有的光致抗蚀剂。 使用C，H和O蚀刻气体组合物，通过第二蚀刻步骤将MTJ图案转移通过剩余的硬掩模层和下面的MTJ堆叠层。

公开(公告)号：US07884433B2

公开(公告)日：2011-02-08

申请号：US12290495

申请日：2008-10-31

申请人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

发明人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

IPC分类号： H01L29/82

CPC分类号： H01L27/228 ,  H01L43/12

摘要： A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.

摘要翻译： 公开了一种STT-MRAM集成方案，其中通过在CMOS着陆焊盘，接触和覆盖VAC的金属（VAM）焊盘上形成中间通孔接触（VAC）来简化MTJ和CMOS金属之间的连接，以及MTJ 在VAM上。 执行双镶嵌工艺，通过设备区域中的VAC / VAM / MTJ堆叠将BIT线金属连接到CMOS着陆焊盘，并通过设备区域外的BIT连接通孔将BIT线连接焊盘连接到CMOS连接焊盘。 VAM焊盘是由Ta，TaN或用作扩散阻挡层的其它导体制成的单层或复合材料，具有用于MTJ形成的高度光滑的表面，并且在化学机械抛光工艺期间提供了与补充介电材料的优异选择性。 每个VAC为500至3000埃厚，以最小化额外的电路电阻并最小化蚀刻负担。

公开(公告)号：US20100109106A1

公开(公告)日：2010-05-06

申请号：US12290495

申请日：2008-10-31

申请人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

发明人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

IPC分类号： H01L29/82 ,  H01L21/00

CPC分类号： H01L27/228 ,  H01L43/12

摘要： A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.

摘要翻译： 公开了一种STT-MRAM集成方案，其中通过在CMOS着陆焊盘，接触和覆盖VAC的金属（VAM）焊盘上形成中间通孔接触（VAC）来简化MTJ和CMOS金属之间的连接，以及MTJ 在VAM上。 执行双镶嵌工艺，通过设备区域中的VAC / VAM / MTJ堆叠将BIT线金属连接到CMOS着陆焊盘，并通过设备区域外的BIT连接通孔将BIT线连接焊盘连接到CMOS连接焊盘。 VAM焊盘是由Ta，TaN或用作扩散阻挡层的其它导体制成的单层或复合材料，具有用于MTJ形成的高度光滑的表面，并且在化学机械抛光工艺期间提供了与补充介电材料的优异选择性。 每个VAC为500至3000埃厚，以最小化额外的电路电阻并最小化蚀刻负担。

公开(公告)号：US20090104718A1

公开(公告)日：2009-04-23

申请号：US11975045

申请日：2007-10-17

申请人： Tom Zhong ,  Rongfu Xiao ,  Chyu-Jiuh Torng ,  Adam Zhong

发明人： Tom Zhong ,  Rongfu Xiao ,  Chyu-Jiuh Torng ,  Adam Zhong

IPC分类号： H01L21/00

CPC分类号： H01L43/12 ,  B82Y10/00 ,  H01L27/228

摘要： A method for forming a MTJ in a STT-MRAM is disclosed in which the easy-axis CD is determined independently of the hard-axis CD. One approach involves two photolithography steps and two etch steps to form a post in a hard mask which is transferred through a MTJ stack of layers by a third etch process. Optionally, the third etch may stop on the tunnel barrier or in the free layer. A second embodiment involves forming a first parallel line pattern on a hard mask layer and transferring the line pattern through the MTJ stack with a first etch step. A planar insulation layer is formed adjacent to the sidewalls in the line pattern and then a second parallel line pattern is formed which is transferred by a second etch through the MTJ stack to form a post pattern. Etch end point may be controlled independently for hard-axis and easy-axis dimensions.

摘要翻译： 公开了一种用于在STT-MRAM中形成MTJ的方法，其中容易轴CD独立于硬轴CD来确定。 一种方法涉及两个光刻步骤和两个蚀刻步骤，以在通过第三蚀刻工艺通过MTJ叠层堆叠的硬掩模中形成柱。 可选地，第三蚀刻可以在隧道势垒上或在自由层中停止。 第二实施例涉及在硬掩模层上形成第一平行线图案，并通过第一蚀刻步骤通过MTJ堆叠传送线图案。 平面绝缘层与线图案中的侧壁相邻地形成，然后形成第二平行线图案，其通过第二次蚀刻通过MTJ叠层转印以形成柱形图案。 蚀刻终点可以独立控制硬轴和易轴尺寸。

公开(公告)号：US07936027B2

公开(公告)日：2011-05-03

申请号：US12006889

申请日：2008-01-07

申请人： Rongfu Xiao ,  Chyu-Jiuh Torng ,  Tom Zhong ,  Witold Kula

发明人： Rongfu Xiao ,  Chyu-Jiuh Torng ,  Tom Zhong ,  Witold Kula

IPC分类号： G11C11/02

CPC分类号： H01L43/12 ,  H01L43/08

摘要： An MTJ cell without footings and free from electrical short-circuits across a tunneling barrier layer is formed by using a Ta hard mask layer and a combination of etches. A first etch patterns the Ta hard mask, while a second etch uses O2 applied in a single high power process at two successive different power levels. A first power level of between approximately 200 W and 500 W removes BARC, photoresist and Ta residue from the first etch, the second power level, between approximately 400 W and 600 W continues an etch of the stack layers and forms a protective oxide around the etched sides of the stack. Finally, an etch using a carbon, hydrogen and oxygen gas completes the etch while the oxide layer protects the cell from short-circuits across the lateral edges of the barrier layer.

摘要翻译： 通过使用Ta硬掩模层和蚀刻的组合，形成没有底脚并且穿过隧道势垒层的电短路的MTJ电池。 第一蚀刻图案Ta硬掩模，而第二蚀刻使用在两个连续的不同功率水平下在单个高功率过程中施加的O2。 在大约200W至500W之间的第一功率电平从第一蚀刻去除BARC，光致抗蚀剂和Ta残留物，第二功率电平在大约400W至600W之间，继续蚀刻叠层，并在其周围形成保护氧化物 蚀刻边的堆叠。 最后，使用碳，氢和氧气的蚀刻完成了蚀刻，而氧化物层保护电池免受横跨阻挡层的侧边缘的短路。