公开(公告)号：US5402388A

公开(公告)日：1995-03-28

申请号：US167489

申请日：1993-12-16

申请人： Tomasz Wojcicki ,  Graham Allan ,  Francis Larochelle

发明人： Tomasz Wojcicki ,  Graham Allan ,  Francis Larochelle

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1072

摘要： The present invention relates to a method of writing or reading a semiconductor random access memory (DRAM or SRAM) having plural sense amplifiers connected to bit lines and having data bus read and write amplifiers, formed of providing a pair of data buses for access by each sense amplifier and each read and write amplifier, reading or writing one data bus while precharging the other data bus during a first read or write cycle, and reading or writing the other data bus while precharging the first data bus in a second read or write cycle following the first read or write cycle.

摘要翻译： 本发明涉及一种写入或读取具有连接到位线的多个读出放大器并具有数据总线读和写放大器的半导体随机存取存储器（DRAM或SRAM）的方法，该放大器由提供一对数据总线构成， 读出放大器和每个读写放大器，在第一个读或写周期期间预先对另一个数据总线进行预充电，读或写一个数据总线，同时在第二个读或写周期预充电第一数据总线时读取或写入另一个数据总线 在第一个读或写周期之后。

公开(公告)号：US5424983A

公开(公告)日：1995-06-13

申请号：US167044

申请日：1993-12-16

申请人： Tomasz Wojcicki ,  Francis Larochelle

发明人： Tomasz Wojcicki ,  Francis Larochelle

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1072

摘要： The present invention relates to an output buffer for driving an output driver of a random access memory (RAM) circuit to either of opposite binary data values from a data source and a clock wherein the relative timing of data and clock signals is variable or uncertain, comprised of a source of data signals having pulses one of which has a rising edge either being earlier than a leading edge of a data pulse, being later than the leading edge of the data pul se, or being in a race condition with the data pulse, a source of data signals, a latency counter for receiving the clock signals and for outputting a latent control, apparatus for summing the latent clock signal and the data pulse, and apparatus for providing a signal to an output driver from the summing apparatus which is in sync with the latent clock signal.

摘要翻译： 本发明涉及一种用于将随机存取存储器（RAM）电路的输出驱动器驱动到来自数据源的相对二进制数据值中的任一者的输出缓冲器和数据和时钟信号的相对定时是可变或不确定的时钟， 包括具有脉冲源的数据信号源，其中一个数据信号具有比数据脉冲的前沿更早的上升沿，比数据脉冲的前沿稍晚，或者处于与数据脉冲的竞争条件 ，数据信号源，用于接收时钟信号并输出​​潜在控制的等待时间计数器，用于对潜时钟信号和数据脉冲进行求和的装置，以及用于从求和装置向输出驱动器提供信号的装置，该装置是 与潜时钟信号同步。