公开(公告)号：US20120127068A1

公开(公告)日：2012-05-24

申请号：US13362568

申请日：2012-01-31

申请人： Tomohiko OTOSE

发明人： Tomohiko OTOSE

IPC分类号： G09G5/00 ,  H03L7/00

CPC分类号： G11C19/28

摘要： In a semiconductor circuit a floating node is set to any voltage by utilizing a control signal applied to a refresh terminal and has a period shorter than that of a clock signal. The circuit includes first and second transistors connected between a first clock terminal and first power supply terminal, third and fourth transistors connected between the refresh terminal and the first power supply terminal, and fifth and sixth transistors connected between a second power supply terminal and the first power supply. Gates of the fourth and fifth transistors are connected to an input terminal, a gate of the third transistor is connected to a second clock terminal, a gate of the first transistor is connected to a node between the fifth and sixth transistors, gates of the second and sixth transistors are connected, and a node between the first and second transistors is connected to an output terminal.

摘要翻译： 在半导体电路中，通过利用施加到刷新端子的控制信号将浮动节点设置为任何电压，并且具有比时钟信号的周期短的周期。 电路包括连接在第一时钟端子和第一电源端子之间的第一和第二晶体管，连接在刷新端子和第一电源端子之间的第三和第四晶体管，以及连接在第二电源端子与第一电源端子之间的第五和第六晶体管 电源。 第四晶体管和第五晶体管的栅极连接到输入端子，第三晶体管的栅极连接到第二时钟端子，第一晶体管的栅极连接到第五和第六晶体管之间的节点，第二晶体管的栅极 并且第六晶体管连接，并且第一和第二晶体管之间的节点连接到输出端子。

公开(公告)号：US20080123799A1

公开(公告)日：2008-05-29

申请号：US11987057

申请日：2007-11-27

申请人： Tomohiko OTOSE

发明人： Tomohiko OTOSE

IPC分类号： G11C19/28 ,  H03L5/00

CPC分类号： G11C19/28

摘要： Disclosed is a semiconductor circuit in which a floating node is set to any voltage by utilizing a control signal which is applied to a refresh terminal and has a period shorter than that of a clock signal. The semiconductor circuit includes first and second transistors connected between a first clock terminal and a first power supply terminal, third and fourth transistors connected between the refresh terminal and the first power supply terminal, and fifth and sixth transistors connected between a second power supply terminal and the first power supply. Gates of the fourth and fifth transistors are connected in common to an input terminal, a gate of the third transistor is connected to a second clock terminal, a gate of the first transistor is connected to a connection node between the fifth and sixth transistors, the gate of the second transistor is connected to the gate of the sixth transistor, and a connection node between the first and second transistors is connected to an output terminal.

摘要翻译： 公开了一种半导体电路，其中通过利用施加到刷新端子并且具有比时钟信号的周期短的周期的控制信号将浮动节点设置为任何电压。 半导体电路包括连接在第一时钟端子和第一电源端子之间的第一和第二晶体管，连接在刷新端子和第一电源端子之间的第三和第四晶体管，以及连接在第二电源端子与第二电源端子之间的第五和第六晶体管， 第一个电源。 第四晶体管和第五晶体管的栅极共同连接到输入端子，第三晶体管的栅极连接到第二时钟端子，第一晶体管的栅极连接到第五和第六晶体管之间的连接节点， 第二晶体管的栅极连接到第六晶体管的栅极，并且第一和第二晶体管之间的连接节点连接到输出端子。

公开(公告)号：US20090115792A1

公开(公告)日：2009-05-07

申请号：US12264377

申请日：2008-11-04

申请人： Tomohiko OTOSE ,  Masamichi Shimoda

发明人： Tomohiko OTOSE ,  Masamichi Shimoda

IPC分类号： G09G5/36 ,  G11C19/28 ,  G11C19/00

CPC分类号： G11C19/28 ,  G09G3/3677

摘要： A device, in which circuit size is small and operation is stable, comprises a plurality of serially connected unit registers (shift registers) in which transfer is controlled by any of three or more clock signals each having a different phase, and a setting signal which determines shift direction; and a selection circuit (switch array) which can select at least one clock signal from the three or more clock signals in accordance with the setting signal; wherein the unit registers are put in a reset state by one clock signal selected by the selection circuit, corresponding to each of the unit registers

摘要翻译： 电路尺寸小且操作稳定的装置包括多个串联的单元寄存器（移位寄存器），其中传输由三个或更多个具有不同相位的时钟信号中的任何一个控制，以及设置信号 确定换档方向; 以及选择电路（开关阵列），其可以根据设置信号从三个或更多个时钟信号中选择至少一个时钟信号; 其中单元寄存器由选择电路选择的与每个单元寄存器对应的一个时钟信号置于复位状态

公开(公告)号：US20090021466A1

公开(公告)日：2009-01-22

申请号：US12174808

申请日：2008-07-17

申请人： Tomohiko OTOSE ,  Masamichi Shimoda

发明人： Tomohiko OTOSE ,  Masamichi Shimoda

IPC分类号： G09G3/36

CPC分类号： G09G3/3674 ,  G09G2310/0283 ,  G09G2340/0492 ,  G11C19/28

摘要： Disclosed is a display apparatus including two scanning circuits of the same configuration and layout, arranged on either sides of the display part. As long as one of the scanning circuits is in operation, the other scanning circuit is in a state in which no output signal is output.

摘要翻译： 公开了一种显示装置，其包括布置在显示部分的两侧上的相同配置和布局的两个扫描电路。 只要其中一个扫描电路工作，另一扫描电路处于不输出输出信号的状态。

公开(公告)号：US20100085294A1

公开(公告)日：2010-04-08

申请号：US12575101

申请日：2009-10-07

申请人： Tomohiko OTOSE

发明人： Tomohiko OTOSE

IPC分类号： G09G3/36 ,  G11C19/00

CPC分类号： G11C19/28 ,  G09G3/3677 ,  G09G2310/0286

摘要： A shift register comprises: a first output circuit controlled by a first clock signal to output a signal to a first output signal line; a second output circuit controlled by a second clock signal with a phase different from a phase of the first clock signal to output a signal to a second output signal line; a first control signal line connected to the first and second output circuits; and a second control signal line connected to the first and second output circuits.

摘要翻译： 移位寄存器包括：由第一时钟信号控制的第一输出电路，以将信号输出到第一输出信号线; 由第二时钟信号控制的第二输出电路，其具有不同于第一时钟信号的相位的相位，以将信号输出到第二输出信号线; 连接到第一和第二输出电路的第一控制信号线; 以及连接到第一和第二输出电路的第二控制信号线。