公开(公告)号：US20090021466A1

公开(公告)日：2009-01-22

申请号：US12174808

申请日：2008-07-17

申请人： Tomohiko OTOSE ,  Masamichi Shimoda

发明人： Tomohiko OTOSE ,  Masamichi Shimoda

IPC分类号： G09G3/36

CPC分类号： G09G3/3674 ,  G09G2310/0283 ,  G09G2340/0492 ,  G11C19/28

摘要： Disclosed is a display apparatus including two scanning circuits of the same configuration and layout, arranged on either sides of the display part. As long as one of the scanning circuits is in operation, the other scanning circuit is in a state in which no output signal is output.

摘要翻译： 公开了一种显示装置，其包括布置在显示部分的两侧上的相同配置和布局的两个扫描电路。 只要其中一个扫描电路工作，另一扫描电路处于不输出输出信号的状态。

公开(公告)号：US08937614B2

公开(公告)日：2015-01-20

申请号：US12264377

申请日：2008-11-04

申请人： Tomohiko Otose ,  Masamichi Shimoda

发明人： Tomohiko Otose ,  Masamichi Shimoda

IPC分类号： G06F3/038 ,  G09G5/00 ,  G11C19/28 ,  G09G3/36

CPC分类号： G11C19/28 ,  G09G3/3677

摘要： A device, in which circuit size is small and operation is stable, comprises a plurality of serially connected unit registers (shift registers) in which transfer is controlled by any of three or more clock signals each having a different phase, and a setting signal which determines shift direction; and a selection circuit (switch array) which can select at least one clock signal from the three or more clock signals in accordance with the setting signal; wherein the unit registers are put in a reset state by one clock signal selected by the selection circuit, corresponding to each of the unit registers

摘要翻译： 电路尺寸小且操作稳定的装置包括多个串联的单元寄存器（移位寄存器），其中传输由三个或更多个具有不同相位的时钟信号中的任何一个控制，以及设置信号 确定换档方向; 以及选择电路（开关阵列），其可以根据设置信号从三个或更多个时钟信号中选择至少一个时钟信号; 其中单元寄存器由选择电路选择的与每个单元寄存器对应的一个时钟信号置于复位状态

公开(公告)号：US20090115792A1

公开(公告)日：2009-05-07

申请号：US12264377

申请日：2008-11-04

申请人： Tomohiko OTOSE ,  Masamichi Shimoda

发明人： Tomohiko OTOSE ,  Masamichi Shimoda

IPC分类号： G09G5/36 ,  G11C19/28 ,  G11C19/00

CPC分类号： G11C19/28 ,  G09G3/3677

摘要： A device, in which circuit size is small and operation is stable, comprises a plurality of serially connected unit registers (shift registers) in which transfer is controlled by any of three or more clock signals each having a different phase, and a setting signal which determines shift direction; and a selection circuit (switch array) which can select at least one clock signal from the three or more clock signals in accordance with the setting signal; wherein the unit registers are put in a reset state by one clock signal selected by the selection circuit, corresponding to each of the unit registers

摘要翻译： 电路尺寸小且操作稳定的装置包括多个串联的单元寄存器（移位寄存器），其中传输由三个或更多个具有不同相位的时钟信号中的任何一个控制，以及设置信号 确定换档方向; 以及选择电路（开关阵列），其可以根据设置信号从三个或更多个时钟信号中选择至少一个时钟信号; 其中单元寄存器由选择电路选择的与每个单元寄存器对应的一个时钟信号置于复位状态

公开(公告)号：US08654056B2

公开(公告)日：2014-02-18

申请号：US13339804

申请日：2011-12-29

申请人： Tomohiko Otose ,  Masamichi Shimoda

发明人： Tomohiko Otose ,  Masamichi Shimoda

IPC分类号： G09G3/36 ,  G06F3/038 ,  G11C19/00

CPC分类号： G09G3/3674 ,  G09G2310/0283 ,  G09G2340/0492 ,  G11C19/28

摘要： Disclosed is a display apparatus including two scanning circuits of the same configuration and layout, arranged on either sides of the display part. As long as one of the scanning circuits is in operation, the other scanning circuit is in a state in which no output signal is output.

摘要翻译： 公开了一种显示装置，其包括布置在显示部分的两侧上的相同配置和布局的两个扫描电路。 只要其中一个扫描电路工作，另一扫描电路处于不输出输出信号的状态。

公开(公告)号：US07889832B2

公开(公告)日：2011-02-15

申请号：US12470788

申请日：2009-05-22

申请人： Tomohiko Otose ,  Masamichi Shimoda

发明人： Tomohiko Otose ,  Masamichi Shimoda

IPC分类号： G11C19/00

CPC分类号： G11C19/28 ,  G09G3/3266 ,  G09G2310/0286 ,  G09G2330/021

摘要： Disclosed is a shift register which includes first transistor connected between a first clock signal terminal and an output terminal, a second transistor with a gate connected to an input terminal and a source connected to a gate of the first transistor, a third transistor with a gate connected to a second clock signal terminal, an inverter with an input connected to the input terminal, a fourth transistor cascode connected to the third transistor with a gate connected to an output of the inverter, a fifth transistor connected between the gate of the first transistor and a power supply terminal, a sixth transistor connected between the fourth transistor and the power supply terminal with a gate connected to the input terminal, and a seventh transistor connected between the output terminal and the power supply terminal, the fifth and seventh transistors having gates connected in common to a connection node of the fourth and the sixth transistors.

摘要翻译： 公开了一种移位寄存器，其包括连接在第一时钟信号端和输出端之间的第一晶体管，具有连接到输入端的栅极的第二晶体管和连接到第一晶体管的栅极的源极，具有栅极的第三晶体管 连接到第二时钟信号端子，具有连接到输入端子的输入的反相器，连接到第三晶体管的第四晶体管共源共栅，栅极连接到反相器的输出，第五晶体管连接在第一晶体管的栅极之间 电源端子，连接在第四晶体管和电源端子之间的第六晶体管，栅极连接到输入端子，第七晶体管连接在输出端子和电源端子之间，第五和第七晶体管具有栅极 共同连接到第四和第六晶体管的连接节点。

公开(公告)号：US20090290677A1

公开(公告)日：2009-11-26

申请号：US12470788

申请日：2009-05-22

申请人： Tomohiko Otose ,  Masamichi Shimoda

发明人： Tomohiko Otose ,  Masamichi Shimoda

IPC分类号： G11C19/00 ,  H02M3/07

CPC分类号： G11C19/28 ,  G09G3/3266 ,  G09G2310/0286 ,  G09G2330/021

摘要： Disclosed is a shift register which includes first transistor connected between a first clock signal terminal and an output terminal, a second transistor with a gate connected to an input terminal and a source connected to a gate of the first transistor, a third transistor with a gate connected to a second clock signal terminal, an inverter with an input connected to the input terminal, a fourth transistor cascode connected to the third transistor with a gate connected to an output of the inverter, a fifth transistor connected between the gate of the first transistor and a power supply terminal, a sixth transistor connected between the fourth transistor and the power supply terminal with a gate connected to the input terminal, and a seventh transistor connected between the output terminal and the power supply terminal, the fifth and seventh transistors having gates connected in common to a connection node of the fourth and the sixth transistors.

摘要翻译： 公开了一种移位寄存器，其包括连接在第一时钟信号端和输出端之间的第一晶体管，具有连接到输入端的栅极的第二晶体管和连接到第一晶体管的栅极的源极，具有栅极的第三晶体管 连接到第二时钟信号端子，具有连接到输入端子的输入的反相器，连接到第三晶体管的第四晶体管共源共栅，栅极连接到反相器的输出，第五晶体管连接在第一晶体管的栅极之间 电源端子，连接在第四晶体管和电源端子之间的第六晶体管，栅极连接到输入端子，第七晶体管连接在输出端子和电源端子之间，第五和第七晶体管具有栅极 共同连接到第四和第六晶体管的连接节点。

公开(公告)号：US08531376B2

公开(公告)日：2013-09-10

申请号：US11438708

申请日：2006-05-22

申请人： Masamichi Shimoda

发明人： Masamichi Shimoda

IPC分类号： G09G3/36

CPC分类号： G11C19/28

摘要： There is disclosed a shift register comprising a bootstrap circuit that outputs a voltage of the supply voltage to the output when the voltage of a first node becomes higher or lower than the supply voltage. The shift register comprises: two or more transistors connected in series to the first node; a device for supplying the voltage to a second node between the transistors such that the voltage between the drains and sources of the transistors becomes below the supply voltage; a first input transistor connected to the first node, and the gate electrode thereof is connected to a first input terminal as well; and an output transistor connected to the output terminal and the clock signal while having the gate electrode connected to the first node, wherein the gate electrode of the output transistor is not opened except for the bootstrap period.

摘要翻译： 公开了一种移位寄存器，包括自举电路，当第一节点的电压变得高于或低于电源电压时，该自举电路向输出端输出电源电压的电压。 移位寄存器包括：与第一节点串联连接的两个或多个晶体管; 用于将电压提供给晶体管之间的第二节点的装置，使得晶体管的漏极和源极之间的电压变得低于电源电压; 连接到第一节点的第一输入晶体管，其栅电极也连接到第一输入端子; 以及输出晶体管，其连接到所述输出端子和所述时钟信号，同时所述栅电极连接到所述第一节点，其中所述输出晶体管的栅极电极除了所述自举周期之外不被打开。

公开(公告)号：US07515150B2

公开(公告)日：2009-04-07

申请号：US10942760

申请日：2004-09-16

申请人： Katsumi Abe ,  Masamichi Shimoda

发明人： Katsumi Abe ,  Masamichi Shimoda

IPC分类号： G09G5/00

CPC分类号： G09G3/3241 ,  G09G3/3275 ,  G09G2300/0417 ,  G09G2300/0842 ,  G09G2310/027

摘要： A semiconductor device is capable of suppressing variations of a current or a voltage to be supplied to an external circuit. The semiconductor device has a plurality of unit areas arrayed in one direction, and components in the unit areas are arranged in the same shape and the same layout in the unit areas. A holding capacitor for holding a voltage is surrounded by an interconnect kept at ground potential. Interconnects at ground potential are inserted in areas where reference current interconnects for supplying reference currents to functional blocks (1-bit DCC circuit regions) and gradation digital data interconnects and storage timing signal interconnects cross each other vertically, the interconnects being disposed between these reference current interconnects, gradation digital data interconnects and storage timing signal interconnects.

摘要翻译： 半导体器件能够抑制要供给到外部电路的电流或电压的变化。 半导体器件具有沿一个方向排列的多个单位区域，并且单位区域中的部件在单位区域中以相同的形状和相同的布局布置。 用于保持电压的保持电容器被保持接地电位的互连件包围。 接地电位互连插入到用于向功能块（1位DCC电路区）提供参考电流的参考电流互连和色阶数字数据互连和存储定时信号互连垂直交叉的区域中，互连设置在这些参考电流 互连，灰度数字数据互连和存储定时信号互连。

公开(公告)号：US20080238384A1

公开(公告)日：2008-10-02

申请号：US12149354

申请日：2008-04-30

申请人： Katsuyuki Fujikura ,  Katsumi Abe ,  Masamichi Shimoda

发明人： Katsuyuki Fujikura ,  Katsumi Abe ,  Masamichi Shimoda

IPC分类号： G05F1/00

CPC分类号： G05F3/262

摘要： A current source circuit includes a voltage output section which outputs a voltage signal; a current source section and a conversion section. The current source section has at least one current source block comprising a plurality of current sources, each of which outputs an output current. The conversion section is provided between the voltage output section and the current source section and outputs a reference current to the plurality of current sources of the at least one current source block based on the voltage signal such that the output current from each of the plurality of current sources is set based on the reference current.

摘要翻译： 电流源电路包括：输出电压信号的电压输出部; 电流源部分和转换部分。 电流源部分具有包括多个电流源的至少一个电流源块，每个电流源输出输出电流。 转换部分设置在电压输出部分和电流源部分之间，并且基于电压信号将参考电流输出到至少一个电流源模块的多个电流源，使得来自多个 电流源基于参考电流设置。

公开(公告)号：US20050062128A1

公开(公告)日：2005-03-24

申请号：US10942760

申请日：2004-09-16

申请人： Katsumi Abe ,  Masamichi Shimoda

发明人： Katsumi Abe ,  Masamichi Shimoda

IPC分类号： H01L51/50 ,  G02F1/163 ,  G09F9/30 ,  G09G3/20 ,  G09G3/30 ,  G09G3/32 ,  H01L27/13 ,  H01L29/00 ,  H05B33/14

CPC分类号： G09G3/3241 ,  G09G3/3275 ,  G09G2300/0417 ,  G09G2300/0842 ,  G09G2310/027

摘要： A semiconductor device is capable of suppressing variations of a current or a voltage to be supplied to an external circuit. The semiconductor device has a plurality of unit areas arrayed in one direction, and components in the unit areas are arranged in the same shape and the same layout in the unit areas. A holding capacitor for holding a voltage is surrounded by an interconnect kept at ground potential. Interconnects at ground potential are inserted in areas where reference current interconnects for supplying reference currents to functional blocks (1-bit DCC circuit regions) and gradation digital data interconnects and storage timing signal interconnects cross each other vertically, the interconnects being disposed between these reference current interconnects, gradation digital data interconnects and storage timing signal interconnects.

摘要翻译： 半导体器件能够抑制要供给到外部电路的电流或电压的变化。 半导体器件具有沿一个方向排列的多个单位区域，并且单位区域中的部件在单位区域中以相同的形状和相同的布局布置。 用于保持电压的保持电容器被保持接地电位的互连件包围。 接地电位互连插入到用于向功能块（1位DCC电路区）提供参考电流的参考电流互连和色阶数字数据互连和存储定时信号互连垂直交叉的区域中，互连设置在这些参考电流 互连，灰度数字数据互连和存储定时信号互连。