公开(公告)号：US08213247B2

公开(公告)日：2012-07-03

申请号：US12618827

申请日：2009-11-16

申请人： Tomomi Naka ,  Hajime Sakata

发明人： Tomomi Naka ,  Hajime Sakata

IPC分类号： G11C29/00

CPC分类号： G11C29/50 ,  G11C29/12005 ,  G11C2029/5006

摘要： A semiconductor memory device includes a plurality of memory cell transistors arranged in a matrix and each configured to store data, and a test circuit configured to output to outside the semiconductor memory device an output signal indicative of an amount of test current flowing through a selected one of the plurality of memory cell transistors, wherein the test circuit includes a plurality of reference cell transistors employed to successively produce varying amounts of currents, a comparison circuit configured to successively compare the amount of test current with each of the varying amounts of currents, and a code generating circuit configured to generate a code indicative of a result of the successive comparisons performed by the comparison circuit, wherein the code is output as the output signal.

摘要翻译： 半导体存储器件包括以矩阵形式布置并分别被配置为存储数据的多个存储单元晶体管，以及测试电路，被配置为向半导体存储器件外部输出指示流过所选择的测试电流量的输出信号 所述多个存储单元晶体管中的所述测试电路包括用于连续产生不同数量电流的多个参考单元晶体管;比较电路，被配置为连续地将所述测试电流的量与所述不同量的电流中的每一个进行比较;以及 代码生成电路，被配置为生成表示由所述比较电路执行的连续比较的结果的代码，其中所述代码被输出作为所述输出信号。