公开(公告)号：US6018796A

公开(公告)日：2000-01-25

申请号：US825479

申请日：1997-03-28

申请人： Masato Suzuki ,  Toru Morikawa ,  Nobuo Higaki ,  Shinya Miyaji

发明人： Masato Suzuki ,  Toru Morikawa ,  Nobuo Higaki ,  Shinya Miyaji

IPC分类号： G06F9/38 ,  G06F15/00

CPC分类号： G06F9/3867

摘要： A data processor comprises a processing unit which processes an instruction in pipeline stages, the number of which is switchable between n and m, m being a larger number than n. The data processor also comprises a switching unit for switching the number of the pipeline stages of the processing unit between n and m. The switching unit comprises an indicating unit for indicating whether the data processor is in a first operating condition or in a second operating condition, depending either on the frequency of the operation clock provided for the data processor or on the power source voltage supplied to the data processor, and a pipeline control unit for ordering a processing unit to operate in n stages under the first operation condition, and for ordering the processing unit to operate in m stages under the second operating condition.

摘要翻译： 数据处理器包括一个处理单元，处理流水线阶段的指令，其数量可在n和m之间切换，m是比n大的数字。 数据处理器还包括用于在n和m之间切换处理单元的流水线级数的切换单元。 切换单元包括指示单元，用于指示数据处理器是处于第一操作状态还是处于第二操作状态，这取决于为数据处理器提供的操作时钟的频率或提供给数据处理器的电源电压 处理器和流水线控制单元，用于在第一操作条件下命令处理单元在n个阶段中操作，并且用于在第二操作条件下命令处理单元以m级操作。

公开(公告)号：US5909565A

公开(公告)日：1999-06-01

申请号：US625627

申请日：1996-03-29

申请人： Toru Morikawa ,  Nobuo Higaki ,  Shinya Miyaji

发明人： Toru Morikawa ,  Nobuo Higaki ,  Shinya Miyaji

IPC分类号： G06F7/00 ,  G06F9/38 ,  G06F15/16

CPC分类号： G06F9/3877

摘要： An information processing device, including a main processor and a coprocessor for processing data according to instructions stored in memory, which is composed of an instruction bus for transmitting instructions from memory to the main processor and coprocessor; a first bus used for transmitting data from the main processor to the coprocessor; a second bus used for transmitting data from the coprocessor to the main processor; instruction detecting means for detecting coprocessor calculation instructions out of the instructions received from memory; operand identifying means for identifying source registers and destination registers specified by operands in a detected instruction; data supplying means for supplying data from the identified source registers to the coprocessor via the first bus; data storing means for storing coprocessor calculation results in the identified destination registers; coprocessor instruction detecting means for detecting coprocessor calculation instructions out of all of the instructions received from the memory; and coprocessor instruction executing means for executing the coprocessor calculation instructions detected by the coprocessor instruction detecting means using data supplied by the first bus and for supplying the calculation result on the second bus.

摘要翻译： 一种信息处理装置，包括主处理器和协处理器，用于根据存储在存储器中的指令来处理数据，该指令由用于从存储器向主处理器和协处理器发送指令的指令总线组成; 用于从主处理器向协处理器发送数据的第一总线; 用于将数据从协处理器传送到主处理器的第二总线; 指令检测装置，用于从存储器接收的指令中检测协处理器计算指令; 用于识别在检测到的指令中由操作数指定的源寄存器和目标寄存器的操作数识别装置; 数据提供装置，用于经由第一总线从识别的源寄存器向协处理器提供数据; 数据存储装置，用于将协处理器计算结果存储在所识别的目的地寄存器中; 协处理器指令检测装置，用于从存储器接收到的所有指令中检测协处理器计算指令; 以及协处理器指令执行装置，用于执行由协处理器指令检测装置检测的协处理器计算指令，使用由第一总线提供的数据并将计算结果提供给第二总线。

公开(公告)号：USRE43729E1

公开(公告)日：2012-10-09

申请号：US13092453

申请日：2011-04-22

申请人： Toru Morikawa ,  Nobuo Higaki ,  Akira Miyoshi ,  Keizo Sumida

发明人： Toru Morikawa ,  Nobuo Higaki ,  Akira Miyoshi ,  Keizo Sumida

IPC分类号： G06F9/302

摘要： A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction “MCSST D1” is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer “0x0000_00FF”. The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is “ON”. The multiplexer 24 outputs one of the maximum value “0x0000_00FF” generated by the constant generator 21, the zero value “0x0000_0000” generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.

摘要翻译： 执行正转换处理的处理器，其将编码数据转换为未编码数据，以及饱和度计算处理，其以高速将值舍入到适当位数。 当正转换饱和度计算指令MCSST D1被解码时，积和结果寄存器6将其保持值输出到路径P1。 比较器22将和积结果寄存器6的保持值的大小与编码的32位整数0x0000_00FF进行比较。 极性判定单元23判断由积分结果寄存器6保持的值的第八位是否为ON。 复用器24输出由常数发生器21产生的最大值0x0000_00FF，由零发生器25产生的零值0x0000_0000和和积结果寄存器6的保持值到数据总线18之一。

公开(公告)号：USRE39121E1

公开(公告)日：2006-06-06

申请号：US10366502

申请日：2003-02-13

申请人： Toru Morikawa ,  Nobuo Higaki ,  Akira Miyoshi ,  Keizo Sumida

发明人： Toru Morikawa ,  Nobuo Higaki ,  Akira Miyoshi ,  Keizo Sumida

IPC分类号： G06F9/302 ,  G06F7/38

CPC分类号： G06F9/3001 ,  G06F7/49921 ,  G06F7/5443 ,  G06F7/57

摘要： A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction “MCSST D1” is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer “0x0000_00FF”. The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is “ON”. The multiplexer 24 outputs one of the maximum value “0x0000_00FF” generated by the constant generator 21, the zero value “0x0000_0000” generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.

摘要翻译： 执行正转换处理的处理器，其将编码数据转换为未编码数据，以及饱和度计算处理，其以高速将值舍入到适当位数。 当正转换饱和度计算指令“MCSST D 1”被解码时，积和结果寄存器6将其保持值输出到路径P 1。 比较器22将和积结果寄存器6的保持值的大小与编码的32位整数“0x0000_00FF”进行比较。 极性判断单元23判断由和积结果寄存器6保持的值的第8位是否为“ON”。 复用器24将由常数发生器21产生的最大值“0x0000_00FF”，由零发生器25产生的零值“0x0000_0000”和和积结果寄存器6的保持值输出到数据总线18中的一个。

公开(公告)号：US5974540A

公开(公告)日：1999-10-26

申请号：US980676

申请日：1997-12-01

申请人： Toru Morikawa ,  Nobuo Higaki ,  Akira Miyoshi ,  Keizo Sumida

发明人： Toru Morikawa ,  Nobuo Higaki ,  Akira Miyoshi ,  Keizo Sumida

IPC分类号： G06F7/544 ,  G06F7/57 ,  G06F9/302 ,  G06F7/38

CPC分类号： G06F9/3001 ,  G06F7/5443 ,  G06F7/57 ,  G06F7/49921

摘要： A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction "MCSST D1" is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer "0x0000.sub.-- 00FF". The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is "ON". The multiplexer 24 outputs one of the maximum value "0x0000.sub.-- 00FF" generated by the constant generator 21, the zero value "0x0000.sub.-- 0000" generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.

摘要翻译： 执行正转换处理的处理器，其将编码数据转换为未编码数据，以及饱和度计算处理，其以高速将值舍入到适当位数。 当正转换饱和度计算指令“MCSST D1”被解码时，积和结果寄存器6将其保持值输出到路径P1。 比较器22将和积结果寄存器6的保持值的大小与编码的32位整数“0x0000-00FF”进行比较。 极性判断单元23判断由和积结果寄存器6保持的值的第8位是否为“ON”。 复用器24输出由常数发生器21产生的最大值“0x0000-00FF”，由零发生器25产生的零值“0x0000-0000”和和积结果寄存器6的保持值之一 数据总线18。

公开(公告)号：US6161171A

公开(公告)日：2000-12-12

申请号：US105212

申请日：1998-06-26

申请人： Toru Morikawa ,  Nobuo Higaki ,  Shinji Ozaki ,  Keisuke Kaneko ,  Satoshi Ogura ,  Masato Suzuki

发明人： Toru Morikawa ,  Nobuo Higaki ,  Shinji Ozaki ,  Keisuke Kaneko ,  Satoshi Ogura ,  Masato Suzuki

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F13/00

CPC分类号： G06F9/3867 ,  G06F12/0855

摘要： A first instruction requiring that a data word should be read out from a data memory and be stored in a certain register in a register set, and then a second instruction requiring that two operands, respectively read out from the register and another register in the register set, should be added are pipeline-processed. In a high-speed mode in which an operation clock having a higher frequency is supplied, a data cache intervened between an instruction execution circuit and the data memory is controlled to supply a data word to a WB (write back) stage of the instruction execution circuit within two cycles with respect to an input address associated with the first instruction. In order to execute the second instruction, the data word is supplied from the WB stage to an EX (operation execution) stage of the instruction execution circuit. In a low-speed mode in which an operation clock having a lower frequency is supplied, the data cache is controlled to supply a data word to an MEM (memory access) stage of the instruction execution circuit within one cycle with respect to an input address associated with the first instruction. In order to execute the second instruction, the data word is bypassed from the MEM stage to the EX stage.

摘要翻译： 需要从数据存储器中读取数据字并将其存储在寄存器组中的特定寄存器中的第一条指令，然后需要分别从寄存器读出的两个操作数和寄存器中的另一个寄存器的第二条指令 设置，应加入管道处理。 在提供具有较高频率的操作时钟的高速模式中，控制指令执行电路和数据存储器之间的数据高速缓冲存储器，以将数据字提供给指令执行的WB（回写）级 电路相对于与第一指令相关联的输入地址在两个周期内。 为了执行第二指令，数据字从WB级提供给指令执行电路的EX（操作执行）级。 在提供具有较低频率的操作时钟的低速模式中，控制数据高速缓冲存储器以相对于输入地址的一个周期内将数据字提供给指令执行电路的MEM（存储器访问）级 与第一条指令相关联。 为了执行第二条指令，将数据字从MEM级旁路到EX级。

公开(公告)号：USRE43145E1

公开(公告)日：2012-01-24

申请号：US11016920

申请日：2004-12-21

申请人： Toru Morikawa ,  Nobuo Higaki ,  Akira Miyoshi ,  Keizo Sumida

发明人： Toru Morikawa ,  Nobuo Higaki ,  Akira Miyoshi ,  Keizo Sumida

IPC分类号： G06F9/302

摘要： A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction “MCSST D1” is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer “0x0000_00FF”. The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is “ON”. The multiplexer 24 outputs one of the maximum value “0x0000_00FF” generated by the constant generator 21, the zero value “0x0000_0000” generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.

摘要翻译： 执行正转换处理的处理器，其将编码数据转换为未编码数据，以及饱和度计算处理，其以高速将值舍入到适当位数。 当正转换饱和度计算指令“MCSST D1”被解码时，积和结果寄存器6将其保持值输出到路径P1。 比较器22将和积结果寄存器6的保持值的大小与编码的32位整数“0x0000_00FF”进行比较。 极性判断单元23判断由和积结果寄存器6保持的值的第8位是否为“ON”。 复用器24将由常数发生器21产生的最大值“0x0000_00FF”，由零发生器25产生的零值“0x0000_0000”和和积结果寄存器6的保持值输出到数据总线18中的一个。

公开(公告)号：US06237084B1

公开(公告)日：2001-05-22

申请号：US09399577

申请日：1999-09-20

申请人： Toru Morikawa ,  Nobuo Higaki ,  Akira Miyoshi ,  Keizo Sumida

发明人： Toru Morikawa ,  Nobuo Higaki ,  Akira Miyoshi ,  Keizo Sumida

IPC分类号： G06F9302

CPC分类号： G06F9/3001 ,  G06F7/49921 ,  G06F7/5443 ,  G06F7/57

摘要： A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction “MCSST D1” is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer “0x0000_00FF”. The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is “ON”. The multiplexer 24 outputs one of the maximum value “0x0000_00FF” generated by the constant generator 21, the zero value “0x0000_0000” generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.

摘要翻译： 执行正转换处理的处理器，其将编码数据转换为未编码数据，以及饱和度计算处理，其以高速将值舍入到适当位数。 当正转换饱和度计算指令“MCSST D1”被解码时，积和结果寄存器6将其保持值输出到路径P1。 比较器22将和积结果寄存器6的保持值的大小与编码的32位整数“0x0000_00FF”进行比较。 极性判断单元23判断由和积结果寄存器6保持的值的第8位是否为“ON”。 复用器24将由常数发生器21产生的最大值“0x0000_00FF”，由零发生器25产生的零值“0x0000_0000”和和积结果寄存器6的保持值输出到数据总线18中的一个。

公开(公告)号：US20050033542A1

公开(公告)日：2005-02-10

申请号：US10899101

申请日：2004-07-27

申请人： Toru Morikawa ,  Kazuhide Watanabe ,  Shinya Miyaji

发明人： Toru Morikawa ,  Kazuhide Watanabe ,  Shinya Miyaji

IPC分类号： G06F11/36 ,  G06F13/00 ,  G06F19/00

CPC分类号： G06F11/3636 ,  G06F11/3652

摘要： A debugger apparatus according to the present embodiment comprises a host, CPU, a plurality of E-memory units (emulation memory units) for storing instructions, and an execution supervision unit. The host traces the instructions to be stored in the E-memory units and transfers the tracing result in the form of an instruction sequence. The execution supervision unit is connected to the CPU, E-memory units, and host. The execution supervision unit individually writes the instruction sequences transferred from the host in the plurality of E-memory units, reads an instruction sequence from one of the plurality of E-memory units in accordance with an instruction address of the CPU to thereby transfer the instruction sequence to the CPU, and outputs an instruction rewriting order to the host when the instruction address of the CPU is irrelevant.

摘要翻译： 根据本实施例的调试器装置包括主机，CPU，用于存储指令的多个E存储器单元（仿真存储器单元）和执行监视单元。 主机跟踪要存储在E-memory单元中的指令，并以指令序列的形式传送跟踪结果。 执行监视单元连接到CPU，电子存储单元和主机。 执行监视单元将从主机传送的指令序列分别写入多个E存储单元中，根据CPU的指令地址从多个E存储器单元之一读取指令序列，从而传送指令 到CPU的序列，并且当CPU的指令地址不相关时，向主机输出指令重写顺序。

公开(公告)号：US07533394B2

公开(公告)日：2009-05-12

申请号：US11110809

申请日：2005-04-21

申请人： Takahiro Yamada ,  Kazuhito Kurita ,  Mikinori Matsuda ,  Toru Morikawa

发明人： Takahiro Yamada ,  Kazuhito Kurita ,  Mikinori Matsuda ,  Toru Morikawa

IPC分类号： G11B17/03

CPC分类号： G11B23/0308 ,  G11B17/046

摘要： A recording and/or reproduction apparatus includes a chassis, a recording and/or reproduction device provided on the chassis so as to perform recording and/or reproduction on a disk cartridge, a cartridge holder for holding the disk cartridge, the cartridge holder being supported to be movable between a disk cartridge insertion/draw-out position and a recording/reproduction position relative to the chassis, an eject lever provided to be movable in the direction for insertion and draw-out of the disk cartridge relative to the chassis, a biasing device for biasing the eject lever in a disk cartridge discharging direction, a shutter unlocking member mounted to one side surface of the cartridge holder, and a shutter unlocking member movement restriction portion provided on the chassis and operable to restrict the shutter lock unlocking member from moving in the direction of spacing away from the one side surface when the cartridge holder is located in the recording/reproduction position.

摘要翻译： 记录和/或再现装置包括：底盘，记录和/或再现装置，设置在底盘上，以便在盘盒上执行记录和/或再现;盒保持器，用于保持盘盒;盒保持器被支撑 能够在盘盒插入/拉出位置和相对于底盘的记录/再现位置之间移动;弹出杆，设置成能够相对于底盘在盘盒的插入和拉出方向上移动; 偏置装置，用于将排出杆偏置在盘盒排出方向上;快门解锁构件，安装到盒保持器的一个侧表面;以及快门解锁构件移动限制部，其设置在底盘上，并且可操作以将快门锁解锁构件 当盒保持器位于记录/再现位置时，在距离一个侧表面的间隔方向上移动。