公开(公告)号：US07123677B2

公开(公告)日：2006-10-17

申请号：US10236377

申请日：2002-09-05

Applicant: Toru Senbongi ,  Kentaro Murayama ,  Makio Kondo

Inventor： Toru Senbongi ,  Kentaro Murayama ,  Makio Kondo

IPC: H04L25/00 ,  H04L7/00 ,  H04L3/24 ,  H04L27/06

CPC classification number: H04L7/0331

Abstract: A sampling data output circuit capable of Accommodating frequency variations includes a converter portion for sampling an input data signal (402) at an oversampling frequency to output, in parallel, a plurality of fundamental signal series (p1, p2, p3, p4), a first circular shifter for receiving the plurality of fundamental signal series and outputting a plurality of first frequency shift signal series having a higher frequency than the fundamental sampling frequency, and a second circular shifter for receiving the plurality of fundamental signal series and outputting a plurality of second frequency shift signal series having a lower frequency than the fundamental sampling frequency. The first and second circular shifters create each of the signal series by selecting a signal sample out of the input fundamental signal series according to a count value of a phase shift cumulative counter and a predetermined rule related to the frequency shift.

Abstract translation: 能够适应频率变化的采样数据输出电路包括用于以过采样频率对输入数据信号（402）进行采样的转换器部分并行地输出多个基本信号序列（p 1，p 2，p 3，p 4），第一圆形移位器，用于接收多个基本信号序列并输出具有比基本采样频率高的频率的多个第一频移信号序列;以及第二圆形移位器，用于接收多个基本信号序列并输出 具有比基本采样频率低的频率的多个第二频移信号序列。 第一和第二圆形移位器通过根据相移累积计数器的计数值和与频移相关的预定规则从输入基本信号序列中选择信号样本来产生每个信号序列。

公开(公告)号：US20050262320A1

公开(公告)日：2005-11-24

申请号：US10977103

申请日：2004-10-29

Applicant: Makio Kondo ,  Naoki Sakaguchi ,  Toru Senbongi

Inventor： Makio Kondo ,  Naoki Sakaguchi ,  Toru Senbongi

IPC: G06F21/24 ,  G06F9/30 ,  G06F12/00 ,  G06F12/14 ,  G06F21/00 ,  H04L9/10

CPC classification number: G06F9/30141 ,  G06F21/71

Abstract: A register unit that is capable of improving data security and minimizing the possibility of data alteration and other manipulations includes multiple registers and a bit layout circuit that is connected to the registers. The bit layout circuit stores a relationship table that defines the relationship between the register bit addresses of all the registers and designated bit addresses of addresses that are designated by an arithmetic unit for a read/write operation. Upon receipt of a write command and its data from the arithmetic unit, the bit layout circuit separates the data into bits, generates storage data by rearranging the data in compliance with the relationship table, and stores the generated data at the register bit addresses of registers indicated in the relationship table.

Abstract translation: 能够提高数据安全性和最小化数据更改和其他操作的可能性的寄存器单元包括连接到寄存器的多个寄存器和位布局电路。 位布局电路存储关系表，其定义了所有寄存器的寄存器位地址和由用于读/写操作的算术单元指定的地址的指定位地址之间的关系。 在从运算单元接收到写命令及其数据后，位布局电路将数据分成比特，通过根据关系表重排数据来生成存储数据，并将生成的数据存储在寄存器的寄存器位地址 在关系表中指出。

公开(公告)号：US06034735A

公开(公告)日：2000-03-07

申请号：US827727

申请日：1997-04-08

Applicant: Toru Senbongi ,  Hitoshi Matsunaga ,  Hiroshi Odanaga

Inventor： Toru Senbongi ,  Hitoshi Matsunaga ,  Hiroshi Odanaga

IPC: H04N9/44 ,  H04N9/45

CPC classification number: H04N9/45

Abstract: A clock generation circuit for a digital video processing apparatus which has a simple structure and can be stably worked in both luminance and color signal systems. A color burst phase error signal indicative of phase difference of a color burst signal is produced on the basis of two color difference signals, a sampling clock signal is generated in accordance with the color burst phase error signal, the sampling clock is divided in order to produce a chrominance subcarrier signal, and the phase of the chrominance subcarrier signal is adjusted in accordance with the color burst phase error signal.

Abstract translation: 一种用于数字视频处理设备的时钟发生电路，其具有简单的结构并且可以在亮度和颜色信号系统中稳定地工作。 基于两个色差信号产生指示色同步信号的相位差的色同步相位误差信号，根据色同步相位误差信号产生采样时钟信号，采样时钟被分割为 产生色度副载波信号，并根据色同步相位误差信号调整色度副载波信号的相位。