公开(公告)号：US07123677B2

公开(公告)日：2006-10-17

申请号：US10236377

申请日：2002-09-05

Applicant: Toru Senbongi ,  Kentaro Murayama ,  Makio Kondo

Inventor： Toru Senbongi ,  Kentaro Murayama ,  Makio Kondo

IPC: H04L25/00 ,  H04L7/00 ,  H04L3/24 ,  H04L27/06

CPC classification number: H04L7/0331

Abstract: A sampling data output circuit capable of Accommodating frequency variations includes a converter portion for sampling an input data signal (402) at an oversampling frequency to output, in parallel, a plurality of fundamental signal series (p1, p2, p3, p4), a first circular shifter for receiving the plurality of fundamental signal series and outputting a plurality of first frequency shift signal series having a higher frequency than the fundamental sampling frequency, and a second circular shifter for receiving the plurality of fundamental signal series and outputting a plurality of second frequency shift signal series having a lower frequency than the fundamental sampling frequency. The first and second circular shifters create each of the signal series by selecting a signal sample out of the input fundamental signal series according to a count value of a phase shift cumulative counter and a predetermined rule related to the frequency shift.

Abstract translation: 能够适应频率变化的采样数据输出电路包括用于以过采样频率对输入数据信号（402）进行采样的转换器部分并行地输出多个基本信号序列（p 1，p 2，p 3，p 4），第一圆形移位器，用于接收多个基本信号序列并输出具有比基本采样频率高的频率的多个第一频移信号序列;以及第二圆形移位器，用于接收多个基本信号序列并输出 具有比基本采样频率低的频率的多个第二频移信号序列。 第一和第二圆形移位器通过根据相移累积计数器的计数值和与频移相关的预定规则从输入基本信号序列中选择信号样本来产生每个信号序列。

公开(公告)号：US20050262320A1

公开(公告)日：2005-11-24

申请号：US10977103

申请日：2004-10-29

Applicant: Makio Kondo ,  Naoki Sakaguchi ,  Toru Senbongi

Inventor： Makio Kondo ,  Naoki Sakaguchi ,  Toru Senbongi

IPC: G06F21/24 ,  G06F9/30 ,  G06F12/00 ,  G06F12/14 ,  G06F21/00 ,  H04L9/10

CPC classification number: G06F9/30141 ,  G06F21/71

Abstract: A register unit that is capable of improving data security and minimizing the possibility of data alteration and other manipulations includes multiple registers and a bit layout circuit that is connected to the registers. The bit layout circuit stores a relationship table that defines the relationship between the register bit addresses of all the registers and designated bit addresses of addresses that are designated by an arithmetic unit for a read/write operation. Upon receipt of a write command and its data from the arithmetic unit, the bit layout circuit separates the data into bits, generates storage data by rearranging the data in compliance with the relationship table, and stores the generated data at the register bit addresses of registers indicated in the relationship table.

Abstract translation: 能够提高数据安全性和最小化数据更改和其他操作的可能性的寄存器单元包括连接到寄存器的多个寄存器和位布局电路。 位布局电路存储关系表，其定义了所有寄存器的寄存器位地址和由用于读/写操作的算术单元指定的地址的指定位地址之间的关系。 在从运算单元接收到写命令及其数据后，位布局电路将数据分成比特，通过根据关系表重排数据来生成存储数据，并将生成的数据存储在寄存器的寄存器位地址 在关系表中指出。

公开(公告)号：US08767268B2

公开(公告)日：2014-07-01

申请号：US13215680

申请日：2011-08-23

Applicant: Hajime Tsukahara ,  Makio Kondo

Inventor： Hajime Tsukahara ,  Makio Kondo

IPC: H04N1/40

CPC classification number: H04N1/00013 ,  H04N1/00031 ,  H04N1/00045 ,  H04N1/0005 ,  H04N1/00055 ,  H04N1/00087 ,  H04N1/1215 ,  H04N1/125 ,  H04N1/193 ,  H04N1/2032 ,  H04N1/401 ,  H04N2201/0081

Abstract: A correction-data generating unit divides, into a matrix of row blocks in a sub scanning direction and column blocks in a main scanning direction, white data on a transfer drum read by a reading unit during a predetermined time period that is shorter than a time period in which the read point of the transfer drum is returned to a position where the reading unit has started reading the first white reference member, calculates, for each column of the matrix, a correction-data candidate value corresponding to a variation ratio of a mean of data of the row blocks in the sub-scanning direction, and determines a minimum value of the calculated correction-data candidate values as the correction data. A shading-data correcting corrects the shading data by using the generated correction data. A shading correcting unit performs shading correction on image data of a document after the correction data is generated.

Abstract translation: 校正数据生成单元将在副扫描方向上的行块和主扫描方向上的列块的矩阵分割为在比时间短的预定时间段期间由读取单元读取的转印鼓上的白色数据 将转印鼓的读取点返回到读取单元已经开始读取第一白色参考构件的位置的周期，对于矩阵的每列计算对应于a的变化比的校正数据候选值 在副扫描方向上的行块的数据的平均值，并且将所计算的校正数据候选值的最小值确定为校正数据。 阴影数据校正通过使用所生成的校正数据校正着色数据。 阴影校正单元在生成校正数据之后对文档的图像数据执行阴影校正。

公开(公告)号：US4811113A

公开(公告)日：1989-03-07

申请号：US63426

申请日：1987-06-18

Applicant: Yoshiaki Ozeki ,  Makio Kondo ,  Hayashi Taniguchi

Inventor： Yoshiaki Ozeki ,  Makio Kondo ,  Hayashi Taniguchi

IPC: G06T9/00 ,  H04N1/419 ,  H04N5/765 ,  H04N7/24 ,  H04N7/12

CPC classification number: H04N1/419 ,  G06T9/005 ,  H04N5/765 ,  H04N7/24

Abstract: An encoding/decoding method for carrying out conversion between run lengths and corresponding run length codes is provided. The run length codes has a format including a first part for storing first information and a second part for storing second information. The first information indicates the length of the code and the second information indicates the corresponding run length. The total number of bits of each of the run length codes is set as an integral multiple of a predetermined number of bits. The present encoding/decoding method is suitable for use in an image processing system, such as a facsimile machine.

Abstract translation: 提供了一种用于执行游程长度和相应游程长度代码之间的转换的编码/解码方法。 运行长度代码具有包括用于存储第一信息的第一部分和用于存储第二信息的第二部分的格式。 第一个信息表示代码的长度，第二个信息表示相应的运行长度。 每个游程长度代码的总位数被设置为预定位数的整数倍。 本编码/解码方法适用于诸如传真机之类的图像处理系统。