公开(公告)号：US06333876B1

公开(公告)日：2001-12-25

申请号：US09536697

申请日：2000-03-28

申请人： Toshiaki Kawasaki ,  Masashi Agata ,  Toshihiro Inokuchi

发明人： Toshiaki Kawasaki ,  Masashi Agata ,  Toshihiro Inokuchi

IPC分类号： G11C700

CPC分类号： G11C29/802 ,  G11C29/848

摘要： The semiconductor memory device of the present invention has: a memory cell array including a plurality of memory cell groups and a redundant cell group having a plurality of redundant cells arranged in parallel with the memory cell groups; a cell selection circuit for allowing one of a plurality of cell selection lines to select a specific memory cell group; a defective cell designation section for outputting defective cell designation signals designating a predetected defective cell out of the plurality of memory cells; and a connection change circuit for electrically disconnecting the cell selection line selecting the memory cell group including the defective cell from the cell selection circuit and outputting an output signal from the cell selection circuit to the redundant cell group. The defective cell designation section includes: a plurality of defective cell designation circuits for outputting designation signals capable of designating the plurality of cell selection lines; and a defective cell designation signal generation circuit for generating and outputting the defective cell designation signals based on the designation signals output from the plurality of defective cell designation circuits. The number of the plurality of defective cell designation circuits is smaller than the number of the plurality of cell selection lines.

摘要翻译： 本发明的半导体存储器件具有：包括多个存储单元组的存储单元阵列和具有与存储单元组并联布置的多个冗余单元的冗余单元组;单元选择电路，用于允许 多个单元选择线，用于选择特定的存储单元组;缺陷单元指定单元，用于输出指定多个存储单元中预先检测的缺陷单元的缺陷单元指定信号;以及连接变换电路，用于电连接单元选择， 存储单元组，其包括来自单元选择电路的缺陷单元，并将来自单元选择电路的输出信号输出到冗余单元组。 有缺陷单元指定部分包括：多个缺陷单元指定电路，用于输出能够指定多个单元选择线的指定信号; 以及有缺陷单元指定信号产生电路，用于基于从多个有缺陷单元指定电路输出的指定信号产生和输出有缺陷单元指定信号。 多个有缺陷单元指定电路的数量小于多个单元选择线的数量。

公开(公告)号：US5901096A

公开(公告)日：1999-05-04

申请号：US34353

申请日：1998-03-04

申请人： Toshihiro Inokuchi ,  Makoto Kojima

发明人： Toshihiro Inokuchi ,  Makoto Kojima

IPC分类号： G11C11/407 ,  G11C11/401 ,  G11C29/02 ,  G11C29/04 ,  G11C29/50 ,  G11C29/00

CPC分类号： G11C29/025 ,  G11C29/02 ,  G11C29/50 ,  G11C11/401 ,  G11C2029/5006

摘要： There is provided disconnecting circuit for disconnecting an internal boosted power supply from a word line. At the time of testing, one of a plurality of word lines is selected therefrom and data on the "Low" level is written in a plurality of memory cells connected to the selected word line. Thereafter, the disconnecting circuit is activated such that the selected word line has high impedance. When there is a leakage current flowing from the word line due to a defect, the potential on the word line lowers rapidly after the word line is disconnected from the internal boosted power supply. Consequently, the data cannot be written properly in the memory cells any more. After a specified period of time has elapsed, data on the "High" level is written sequentially in the memory cells connected to the selected word line. Then, the same word line is selected again such that the data written in the memory cells connected to the word line is read therefrom. If the read data is on the "Low" level and erroneous, it follows that the data on the "High" level has not been written successfully. Therefore, it is judged that there is a leakage current flowing from the word line. In this manner, both testing time and testing cost can be reduced. Since a minimal leakage current that has conventionally been difficult to detect can be detected, testing ensures the removal of a potential defect becoming more evident as the semiconductor memory deteriorates with time.

摘要翻译： 提供了用于断开内部升压的电源与字线的断开电路。 在测试时，从其中选择多个字线中的一个，并且将“低”电平上的数据写入连接到所选字线的多个存储器单元中。 此后，断开电路被激活，使得所选择的字线具有高阻抗。 当由于缺陷而导致从字线流出的漏电流时，字线从内部升压电源断开之后，字线上的电位迅速下降。 因此，无法再将数据写入存储器单元。 在指定的时间段过去之后，“High”电平上的数据被顺序地写入连接到所选字线的存储单元中。 然后，再次选择相同的字线，从而读取写入连接到字线的存储单元中的数据。 如果读取数据处于“低”电平并且错误，则“高”电平上的数据未成功写入。 因此，判断有从字线流出的漏电流。 以这种方式，可以减少测试时间和测试成本。 由于可以检测到传统上难以检测的最小泄漏电流，因此随着时间的推移半导体存储器的劣化，测试确保了潜在缺陷的去除变得更加明显。