公开(公告)号：US20200294554A1

公开(公告)日：2020-09-17

申请号：US16557475

申请日：2019-08-30

Applicant: Toshiba Memory Corporation

Inventor： Takayuki KAKEGAWA ,  Shinya NAITO ,  Masaki KONDO ,  Takashi KURUSU ,  Hiroshi TAKEDA ,  Nayuta KARIYA

IPC: G11C5/06 ,  H01L27/11556 ,  H01L27/11524

Abstract: A semiconductor memory device according to an embodiment includes a substrate, first and second conductive layers, and a first pillar. The first conductive layer is provided above the substrate and includes a first N-type semiconductor region and a first P-type semiconductor region. The second conductive layers are provided above the first conductive layer and stacked at intervals. The first pillar includes a first semiconductor layer and a first insulating layer. The first semiconductor layer is provided through the second conductive layers and is in contact with each of the first N-type semiconductor region and the first P-type semiconductor region. The first insulating layer is provided between the first semiconductor layer and the second conductive layers.