公开(公告)号：US20200251490A1

公开(公告)日：2020-08-06

申请号：US16522730

申请日：2019-07-26

Applicant: Toshiba Memory Corporation

Inventor： Sota MATSUMOTO ,  Junichi SHIBATA ,  Takahito NISHIMURA ,  Kazuhiro WASHIDA

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: A semiconductor memory device according to an embodiment includes, a stacked portion and a pillar. The stacked portion is provided in a first region including a memory cell and in a second region. The stacked portion includes first and second conductive layers and a first insulating layer. The first conductive layers are stacked in a first direction. The second conductive layers are stacked in the first direction above the first conductive layers. The first insulating layer is provided between an uppermost first conductive layer and a lowermost second conductive layer. The pillar penetrates the first and second conductive layers and the first insulating layer. A thickness of the first insulating layer is greater in the