公开(公告)号：US20200294958A1

公开(公告)日：2020-09-17

申请号：US16541398

申请日：2019-08-15

Applicant: Toshiba Memory Corporation

Inventor： Junichi SHIBATA

IPC: H01L23/00 ,  H01L25/18 ,  H01L25/065 ,  H01L25/00

Abstract: In one embodiment, a semiconductor device includes a first wafer or a first chip including a first insulator and a first pad. The device further includes a second wafer or a second chip including a second insulator in contact with the first insulator, and a second pad opposed to the first pad and electrically connected to the first pad. Moreover, the first insulator includes a first trench extending to the first pad, and/or the second insulator includes a second trench extending to the second pad.

公开(公告)号：US20190214268A1

公开(公告)日：2019-07-11

申请号：US16126055

申请日：2018-09-10

Applicant: Toshiba Memory Corporation

Inventor： Masakazu SAWANO ,  Takahiro TOMIMATSU ,  Junichi SHIBATA ,  Hideki INOKUMA ,  Hisashi KATO ,  Kenta YOSHINAGA

IPC: H01L21/311 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582

Abstract: According to one embodiment, a semiconductor device includes: a first stack above a substrate and including insulation layers and conductive layers alternately stacked in a first direction, the first stack including a staircase-shaped portion in an end portion of the first stack in a second direction parallel to a main face of the substrate, the staircase-shaped portion including steps and terraces corresponding to the conductive layers, at least a part of the steps having arc shape curved along a third direction crossing the second direction; and a second stack above the substrate and including first and second layers stacked in the first direction. In the second and/or third direction, a dimension of the first stack is larger than a dimension of the second stack.

公开(公告)号：US20200251490A1

公开(公告)日：2020-08-06

申请号：US16522730

申请日：2019-07-26

Applicant: Toshiba Memory Corporation

Inventor： Sota MATSUMOTO ,  Junichi SHIBATA ,  Takahito NISHIMURA ,  Kazuhiro WASHIDA

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: A semiconductor memory device according to an embodiment includes, a stacked portion and a pillar. The stacked portion is provided in a first region including a memory cell and in a second region. The stacked portion includes first and second conductive layers and a first insulating layer. The first conductive layers are stacked in a first direction. The second conductive layers are stacked in the first direction above the first conductive layers. The first insulating layer is provided between an uppermost first conductive layer and a lowermost second conductive layer. The pillar penetrates the first and second conductive layers and the first insulating layer. A thickness of the first insulating layer is greater in the