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公开(公告)号:US20090070981A1
公开(公告)日:2009-03-19
申请号:US12209435
申请日:2008-09-12
CPC分类号: F16B21/18 , Y10T29/49 , Y10T29/49826 , Y10T29/4984 , Y10T29/53 , Y10T29/53383 , Y10T29/54 , Y10T403/45 , Y10T428/12 , Y10T428/12326 , Y10T428/24025
摘要: The present invention includes a mounting structure for mounting a component between a first member and a second member. According to the mounting structure, the component is first placed on a surface of the first member. Then, the second member is fitted with the component by a fitting device, so that the component is positioned relative to the second member. Thereafter, the component is fixed in position relative to the first member by a joint device.
摘要翻译: 本发明包括用于将部件安装在第一部件和第二部件之间的安装结构。 根据安装结构,首先将部件放置在第一部件的表面上。 然后,第二构件通过装配装置安装在构件上,使得构件相对于第二构件定位。 此后,通过接头装置将部件相对于第一部件固定在适当位置。
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公开(公告)号:US08572828B2
公开(公告)日:2013-11-05
申请号:US12209435
申请日:2008-09-12
IPC分类号: B21D39/03
CPC分类号: F16B21/18 , Y10T29/49 , Y10T29/49826 , Y10T29/4984 , Y10T29/53 , Y10T29/53383 , Y10T29/54 , Y10T403/45 , Y10T428/12 , Y10T428/12326 , Y10T428/24025
摘要: The present invention includes a mounting structure for mounting a component between a first member and a second member. According to the mounting structure, the component is first placed on a surface of the first member. Then, the second member is fitted with the component by a fitting device, so that the component is positioned relative to the second member. Thereafter, the component is fixed in position relative to the first member by a joint device.
摘要翻译: 本发明包括用于将部件安装在第一部件和第二部件之间的安装结构。 根据安装结构,首先将部件放置在第一部件的表面上。 然后,第二构件通过装配装置安装在构件上,使得构件相对于第二构件定位。 此后,通过接头装置将部件相对于第一部件固定在适当位置。
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公开(公告)号:US5016165A
公开(公告)日:1991-05-14
申请号:US142949
申请日:1988-01-12
IPC分类号: G06F13/28 , G06F13/30 , G06F13/362
CPC分类号: G06F13/30
摘要: A direct memory access (DMA) controlled system which performs DMA data transfer between a main memory, a cache memory, and disk memories while exchanging DMA transfer requests and acknowledgements among disk control units, a memory-to-memory transfer control unit, and a common DMA control unit. The data transfer speed between the main memory and the cache memory is variable according to the load condition of the DMA control unit for the disk memories, enabling the transfer capability of the DMA control unit to be kept at a continually high level.
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公开(公告)号:US4374410A
公开(公告)日:1983-02-15
申请号:US064725
申请日:1979-08-08
申请人: Toshihiro Sakai , Tetsuji Kuhara
发明人: Toshihiro Sakai , Tetsuji Kuhara
CPC分类号: G06F12/0292
摘要: In a data processing system in which a data processing unit has an M-bit address register and is connected via an N-bit address bus with a memory (where N
摘要翻译: 在其中数据处理单元具有M位地址寄存器并且经由N位地址总线与存储器(其中N
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