公开(公告)号：US5168566A

公开(公告)日：1992-12-01

申请号：US825334

申请日：1992-01-27

申请人： Masaru Kuki ,  Toshimitsu Nakade ,  Hirotake Hayashi ,  Takaaki Uno

发明人： Masaru Kuki ,  Toshimitsu Nakade ,  Hirotake Hayashi ,  Takaaki Uno

IPC分类号： G06F9/46 ,  G06F9/48

CPC分类号： G06F9/4812 ,  G06F9/3851 ,  G06F9/463 ,  G06F9/4881

摘要： A computer peripheral device incorporating a multi-task control device which is extremely useful for such programs controlling the microcomputer system. In particular, the multi-task control device effectively controls a plurality of tasks executed by the CPU by using means other than the CPU including such means for controlling operations needed for comparing priority orders between a plurality of tasks, and the other means for generating interrupt operations from this control device against the CPU needed for switching tasks being executed in accordance with the result of the priority comparative operations.

摘要翻译： 一种包含多任务控制装置的计算机外围装置，其对于控制微机系统的这种程序非常有用。 特别地，多任务控制装置通过使用包含这种用于控制多个任务之间的优先顺序所需的操作的装置的CPU以外的装置来有效地控制由CPU执行的多个任务，另一个用于产生中断的装置 根据优先级比较操作的结果，从该控制装置对CPU执行切换任务所需的操作。

公开(公告)号：US4847751A

公开(公告)日：1989-07-11

申请号：US59192

申请日：1987-06-08

申请人： Toshimitsu Nakade ,  Masaru Kuki ,  Takaaki Uno

发明人： Toshimitsu Nakade ,  Masaru Kuki ,  Takaaki Uno

IPC分类号： G06F9/46 ,  G06F9/48 ,  G06F15/16

CPC分类号： G06F9/4881

摘要： In a microcomputer system, having independently programmed tasks and a master control processing unit (CPU), tasks can be switched independent of the master CPU through the use of a multi-task support processor which may, for example, be connected to the microcomputer system via an input/output (I/O) port. The multi-task support processor includes a memory for storing task control programs, a data memory and task control memory, a timer, a controller for controlling multi-task operations, and a master CPU interface element. Tasks including task control commands are stored in a memory for execution by the master CPU. The master CPU, upon encountering a task control command, sends that command to the multi-task support processor which becomes activated to control the switching and communications between the tasks under the direction of the received task control command, so that tasking control may be performed independent of the master CPU.

摘要翻译： 在具有独立编程任务的微机系统和主控制处理单元（CPU）中，可以通过使用多任务支持处理器来独立于主CPU来切换任务，所述多任务支持处理器可以例如连接到微机系统 通过输入/输出（I / O）端口。 多任务支持处理器包括用于存储任务控制程序的存储器，数据存储器和任务控制存储器，定时器，用于控制多任务操作的控制器和主CPU接口元件。 包括任务控制命令的任务存储在存储器中以供主CPU执行。 主CPU在遇到任务控制命令时将该命令发送到被激活的多任务支持处理器，以控制在接收的任务控制命令的指导下的任务之间的切换和通信，从而可以执行任务控制 独立于主CPU。

公开(公告)号：US5287318A

公开(公告)日：1994-02-15

申请号：US836023

申请日：1992-02-14

申请人： Masaru Kuki ,  Yukio Kitaguchi

发明人： Masaru Kuki ,  Yukio Kitaguchi

IPC分类号： G11C17/00 ,  G11C16/16 ,  G11C29/00 ,  G11C29/12 ,  G11C29/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00 ,  G11C16/00

CPC分类号： G11C16/16

摘要： In a flash-type electrically erasable programmable read-only memory (EEPROM), the erasure block decoder provided in the row decoder outputs a signal for simultaneously driving half the erasure line drivers in the erasure line driver array, or a signal for simultaneously driving the other half of the erasure line drivers in the erasure line driver array, according to an externally applied address signal. Therefore, the erasure operation test of all the blocks corresponding one-to-one to the erasure line drivers can be completed in two erasure operations, one for each corresponding half of the memory.

摘要翻译： 在闪存式电可擦除可编程只读存储器（EEPROM）中，行解码器中提供的擦除块解码器输出用于同时驱动擦除线驱动器阵列中的一半擦除线驱动器的信号，或者用于同时驱动 根据外部施加的地址信号，擦除线驱动器阵列中的擦除线驱动器的另一半。 因此，可以在两次擦除操作中完成与擦除线驱动器一一对应的所有块的擦除操作测试，每个对应于存储器的相应一半。