公开(公告)号：US06791387B1

公开(公告)日：2004-09-14

申请号：US10650368

申请日：2003-08-27

申请人： Tsin-Yuan Chang ,  Hao-Yung Lo ,  Shao-Sheng Yang

发明人： Tsin-Yuan Chang ,  Hao-Yung Lo ,  Shao-Sheng Yang

IPC分类号： H03K3037

CPC分类号： H03K3/037 ,  H03K3/012

摘要： A feedback latch circuit includes a first logic OR gate for performing a logic OR operation upon a clock input signal and a latch output, a first logic AND gate for performing a logic AND operation upon output of the first logic OR gate and a data input signal, a second logic AND gate for performing a logic AND operation upon a complementary clock input signal and the latch output, and a second logic OR gate for performing a logic OR operation upon outputs of the first and second logic AND gates to result in the latch output that is provided to the first logic OR gate and the second logic AND gate. The complementary clock input signal received by the second logic AND gate complements the clock input signal received by the first logic OR gate.

摘要翻译： 反馈锁存电路包括用于在时钟输入信号和锁存器输出端执行逻辑或运算的第一逻辑“或”门，用于在第一逻辑或门输出时执行逻辑与运算的第一逻辑与门和数据输入信号 ，用于对互补时钟输入信号和所述锁存器输出执行逻辑与运算的第二逻辑与门，以及用于在所述第一和第二逻辑与门的输出上执行逻辑或运算以产生所述锁存器的第二逻辑或门 输出提供给第一逻辑或门和第二逻辑与门。 由第二逻辑与门接收的互补时钟输入信号补充由第一逻辑或门接收的时钟输入信号。