Bistable display device and driving circuit

    公开(公告)号:US10923011B2

    公开(公告)日:2021-02-16

    申请号:US16661992

    申请日:2019-10-23

    摘要: The disclosure provides a bistable display device and a driving circuit. The bistable display device includes a display panel and the above-described driving circuit, wherein the driving circuit includes a source driver, a first image buffer, a second image buffer, and a timing controller. The source driver is coupled to the display panel to drive the display panel according to a pixel signal. The timing controller is coupled to the first image buffer, the second image buffer, and the source driver. The timing controller alternately selects a first image signal temporarily stored in the first image buffer and a second image signal temporarily stored in the second image buffer as a current image signal and a previous image signal. The timing controller performs a look-up mechanism based on the current image signal and the previous image signal to generate the pixel signal.

    Timing controller, display apparatus, and operation method thereof

    公开(公告)号:US10923081B2

    公开(公告)日:2021-02-16

    申请号:US16408451

    申请日:2019-05-09

    摘要: A timing controller, a display apparatus, and an operation method thereof are provided. The display apparatus includes a display panel and a timing controller. The timing controller includes a refresh mark controller and a pixel controller. The refresh mark controller includes a refresh mark table, and a plurality of refresh marks in the refresh mark table correspond to a plurality of sub-regions of a display region in the display panel. The refresh mark controller determines whether the sub-regions need to be refreshed according to an image signal and responds to a specific sub-region required to be refreshed to adjust a specific refresh mark according to a mapping ratio. The pixel controller sequentially looks up whether the refresh marks in the refresh mark table are adjusted, obtains the sub-regions corresponding to the adjusted refresh marks according to the mapping ratio, and performs a pixel refresh operation to the sub-regions.

    TIMING CONTROLLER, DISPLAY APPARATUS, AND OPERATION METHOD THEREOF

    公开(公告)号:US20200258476A1

    公开(公告)日:2020-08-13

    申请号:US16408451

    申请日:2019-05-09

    摘要: A timing controller, a display apparatus, and an operation method thereof are provided. The display apparatus includes a display panel and a timing controller. The timing controller includes a refresh mark controller and a pixel controller. The refresh mark controller includes a refresh mark table, and a plurality of refresh marks in the refresh mark table correspond to a plurality of sub-regions of a display region in the display panel. The refresh mark controller determines whether the sub-regions need to be refreshed according to an image signal and responds to a specific sub-region required to be refreshed to adjust a specific refresh mark according to a mapping ratio. The pixel controller sequentially looks up whether the refresh marks in the refresh mark table are adjusted, obtains the sub-regions corresponding to the adjusted refresh marks according to the mapping ratio, and performs a pixel refresh operation to the sub-regions.

    COMPUTING DEVICE, OPERATION METHOD OF COMPUTING DEVICE AND SYSTEM ON CHIP

    公开(公告)号:US20240061711A1

    公开(公告)日:2024-02-22

    申请号:US18156357

    申请日:2023-01-18

    IPC分类号: G06F9/50 G06F9/48 G06F15/80

    摘要: A computing device, an operation method of the computing device, and a system on chip are provided. The computing device includes an operator and a resource allocation manager. The operator includes multiple arithmetic units. The resource allocation manager is coupled to the operator and allocates the arithmetic units to a deep learning accelerator and a vector processor for use according to an amount of calculation of the deep learning accelerator and an amount of calculation of the vector processor. The operator receives a first operation request and a second operation request from the deep learning accelerator and the vector processor respectively, uses a first arithmetic unit group of the arithmetic units to perform a calculation of the first operation request, and uses a second arithmetic unit group of the arithmetic units to perform a calculation of the second operation request according to an allocation result.

    Data preserving method and data accessing method for non-volatile memory
    5.
    发明授权
    Data preserving method and data accessing method for non-volatile memory 有权
    用于非易失性存储器的数据保存方法和数据访问方法

    公开(公告)号:US08051339B2

    公开(公告)日:2011-11-01

    申请号:US12015484

    申请日:2008-01-16

    IPC分类号: G11C29/00

    CPC分类号: G06F11/1068 G11C2029/0411

    摘要: A data preserving method and a data accessing method for a non-volatile memory are provided. In the data preserving method, a data is checked according to an error correcting code (ECC) to obtain an error bit number of the data. When the error bit number is greater than a threshold, the data is moved from a first memory unit to a second memory unit and is corrected according to the ECC. Thereby, the data stability of the non-volatile memory is improved.

    摘要翻译: 提供了一种用于非易失性存储器的数据保存方法和数据访问方法。 在数据保存方法中,根据纠错码(ECC)检查数据,以获得数据的错误位数。 当错误位数大于阈值时,数据从第一存储器单元移动到第二存储器单元,并根据ECC进行校正。 从而提高了非易失性存储器的数据稳定性。

    Class-D amplifier and multi-level output signal generated method thereof
    6.
    发明授权
    Class-D amplifier and multi-level output signal generated method thereof 失效
    D类放大器及其多电平输出信号产生方法

    公开(公告)号:US07675361B2

    公开(公告)日:2010-03-09

    申请号:US12025055

    申请日:2008-02-04

    IPC分类号: H03F3/217

    CPC分类号: H03F3/217

    摘要: A class-D amplifier and a method of generating a multi-level output signal thereof are provided. The class-D amplifier includes a controlling logic circuit and an output module. The controlling logic circuit analyzes the amplitude of an input signal to generate a voltage modifying signal. A power supply provides a voltage according to the voltage modifying signal. The controlling logic circuit generates controlling signals according to the input signal. The output module generates an output signal to drive a load according to the voltage and the controlling signals. In other words, the resolution of the amplitude of the output signal is increased by modifying the voltage, and a signal to noise ratio is then increased.

    摘要翻译: 提供了D类放大器和一种产生其多电平输出信号的方法。 D类放大器包括控制逻辑电路和输出模块。 控制逻辑电路分析输入信号的幅度以产生电压修正信号。 电源根据电压修正信号提供电压。 控制逻辑电路根据输入信号产生控制信号。 输出模块根据电压和控制信号产生输出信号来驱动负载。 换句话说,通过修改电压来增加输出信号幅度的分辨率,然后增加信噪比。

    Authentication system and authentication method

    公开(公告)号:US11509655B2

    公开(公告)日:2022-11-22

    申请号:US16894889

    申请日:2020-06-08

    摘要: An authentication system and an authentication method are provided. The electronic device of the authentication system includes a controller, a processor and a key module, wherein the processor performs an application program. In a binding phase, the application device generates a digest file according to key factor information and a selection strategy, and stores the digest file in a digest table of the electronic device. In a checking phase, the application program determines whether the controller corresponds to a binding device according to the digest file and the key factor information. If the controller corresponded to the binding device, in an authentication phase, the controller performs an authentication operation of a U2F service with a server device according to the digest file corresponding to the binding device in response to a pressing of the key module.

    CLASS-D AMPLIFIER AND MULTI-LEVEL OUTPUT SIGNAL GENERATED METHOD THEREOF
    8.
    发明申请
    CLASS-D AMPLIFIER AND MULTI-LEVEL OUTPUT SIGNAL GENERATED METHOD THEREOF 失效
    CLASS-D放大器和多级输出信号生成方法

    公开(公告)号:US20090146737A1

    公开(公告)日:2009-06-11

    申请号:US12025055

    申请日:2008-02-04

    IPC分类号: H03F3/217

    CPC分类号: H03F3/217

    摘要: A class-D amplifier and a method of generating a multi-level output signal thereof are provided. The class-D amplifier includes a controlling logic circuit and an output module. The controlling logic circuit analyzes the amplitude of an input signal to generate a voltage modifying signal. A power supply provides a voltage according to the voltage modifying signal. The controlling logic circuit generates controlling signals according to the input signal. The output module generates an output signal to drive a load according to the voltage and the controlling signals. In other words, the resolution of the amplitude of the output signal is increased by modifying the voltage, and a signal to noise ratio is then increased.

    摘要翻译: 提供了D类放大器和一种产生其多电平输出信号的方法。 D类放大器包括控制逻辑电路和输出模块。 控制逻辑电路分析输入信号的幅度以产生电压修正信号。 电源根据电压修正信号提供电压。 控制逻辑电路根据输入信号产生控制信号。 输出模块根据电压和控制信号产生输出信号来驱动负载。 换句话说,通过修改电压来增加输出信号幅度的分辨率,然后增加信噪比。

    DATA PRESERVING METHOD AND DATA ACCESSING METHOD FOR NON-VOLATILE MEMORY
    9.
    发明申请
    DATA PRESERVING METHOD AND DATA ACCESSING METHOD FOR NON-VOLATILE MEMORY 有权
    用于非易失性存储器的数据保存方法和数据访问方法

    公开(公告)号:US20090125764A1

    公开(公告)日:2009-05-14

    申请号:US12015484

    申请日:2008-01-16

    IPC分类号: G11C29/00

    CPC分类号: G06F11/1068 G11C2029/0411

    摘要: A data preserving method and a data accessing method for a non-volatile memory are provided. In the data preserving method, a data is checked according to an error correcting code (ECC) to obtain an error bit number of the data. When the error bit number is greater than a threshold, the data is moved from a first memory unit to a second memory unit and is corrected according to the ECC. Thereby, the data stability of the non-volatile memory is improved.

    摘要翻译: 提供了一种用于非易失性存储器的数据保存方法和数据访问方法。 在数据保存方法中,根据纠错码(ECC)检查数据,以获得数据的错误位数。 当错误位数大于阈值时,数据从第一存储器单元移动到第二存储器单元,并根据ECC进行校正。 从而提高了非易失性存储器的数据稳定性。

    Control device and control method for memory
    10.
    发明授权
    Control device and control method for memory 有权
    存储器的控制装置和控制方法

    公开(公告)号:US07516282B2

    公开(公告)日:2009-04-07

    申请号:US11530025

    申请日:2006-09-08

    IPC分类号: G06F12/00

    摘要: A control device for a memory is provided. The control device includes a micro-control unit (MCU), a command queue, a command sequencer, and a table. The control device is coupled to the memory and is used for controlling the memory to execute an operation. In which, the MCU outputs a control signal according to the operation. The command sequencer sequentially stores command sets required by the execution of the operation according to the control signal, and each command set includes plural commands. The command queue sequentially stores command set contents according to the order of the corresponding command sets. The table stores a target address of the memory required by the execution of the operation.

    摘要翻译: 提供了一种用于存储器的控制装置。 控制装置包括微控制单元(MCU),命令队列,命令定序器和表。 控制装置耦合到存储器,并用于控制存储器以执行操作。 其中,MCU根据操作输出控制信号。 命令定序器根据控制信号依次存储执行操作所需的命令集,并且每个命令集包括多个命令。 命令队列根据相应命令集的顺序依次存储命令集内容。 该表存储执行操作所需的内存的目标地址。