公开(公告)号：US20030191999A1

公开(公告)日：2003-10-09

申请号：US10407088

申请日：2003-04-04

Applicant: U.S. PHILIPS CORPORATION

Inventor： Richard Petrus Kleihorst ,  Renatus Josephus Van Der Vleuten ,  Nico Frits Benschop ,  Geeke Muurling

IPC: G06F011/00 ,  G01R031/28

CPC classification number: G06F11/085 ,  H03M13/00

Abstract: Errors are corrected that occur in the operation of a combinatorial logic circuit in an integrated circuit. The combinatorial circuit computes a vector of intermediate signals from the input signal. The combinatorial logic circuit is designed so that, when the combinatorial logic circuit operates without error, the vector belongs to an error correcting code, not being a repetition code. The combinatorial logic circuit comprises combinatorial logic sections, each for computing a respective one of the intermediate signals independently from the other sections. An error correction circuit computes an output signal from the vector, with a computation that maps erroneous vectors to the output signal for a nearest correct vector from the error correcting code when these erroneous vectors differ from the correct vector in less than a predetermined number of the intermediate signals.