公开(公告)号：US20010015475A1

公开(公告)日：2001-08-23

申请号：US09782662

申请日：2001-02-13

Applicant: U.S. PHILIPS CORPORATION.

Inventor： David Sharples

IPC: H01L027/06 ,  H01L029/76 ,  H01L027/102

CPC classification number: H01L27/0761 ,  H01L24/32 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A semiconductor device comprises a semiconductor body (10) in and on which a power transistor (T; 1, 2, 3) and a suppression diode (D; 100) are integrated. A diode junction (40; 40null) is present between the back metallisation (22) and the adjacent region (2) of the power transistor so as to provide the diode in series with this region (2) and adjacent to the back surface (12) of the body. This diode junction (40; 40null) opposes the p-n junction (42) between the collector or drain region (2) of the transistor and its base region (3), so as to suppress reverse current flow in the transistor. The higher doped part (2b) of the adjacent transistor region (2) is sufficiently thick as to prevent any minority charge carriers injected by the diode junction (40; 40null) from reaching the p-n junction (42) with the base region (3). The diode junction may be a p-n junction (40) or a Schottky barrier (40null). This transistor-diode configuration also permits an anti-parallel diode (D3) to be mounted side-by-side with the power transistor in the same device package (50-53).

Abstract translation: 半导体器件包括其上集成有功率晶体管（T; 1,2,3）和抑制二极管（D; 100）的半导体本体（10）。 在功率晶体管的后金属化（22）和相邻区域（2）之间存在二极管结（40; 40'），以便提供二极管与该区域（2）串联并且邻近背表面 12）身体。 该二极管结（40; 40'）与晶体管的集电极或漏极区（2）与其基极区（3）之间的p-n结（42）相对，从而抑制晶体管中的反向电流流动。 相邻晶体管区域（2）的较高掺杂部分（2b）足够厚，以防止由二极管结（40; 40'）注入的任何少数电荷载体与基极区域（3）到达pn结（42） ）。 二极管结可以是p-n结（40）或肖特基势垒（40'）。 该晶体管二极管配置还允许反并联二极管（D3）与功率晶体管并排安装在同一器件封装（50-53）中。