公开(公告)号：US20180204848A1

公开(公告)日：2018-07-19

申请号：US15405324

申请日：2017-01-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： HAN WANG ,  Xian Feng Du

IPC: H01L27/11568 ,  H01L29/792 ,  H01L29/49

CPC classification number: H01L27/11568 ,  H01L29/4916 ,  H01L29/792

Abstract: A semiconductor memory cell structure includes a substrate, a tunnel dielectric layer formed on the substrate, a blocking dielectric layer formed on the substrate, a control gate formed on the blocking dielectric layer, and a tri-layered charge-trapping layer sandwiched between the tunnel dielectric layer and the blocking dielectric layer. Furthermore, the tri-layered charge-trapping layer includes a bottom nitride layer formed on the substrate, a top nitride layer formed on the bottom nitride layer, and a middle nitride layer sandwiched between the bottom nitride layer and the top nitride layer. The bottom nitride layer includes a first nitride concentration, the top nitride layer includes a second nitride concentration, and the middle nitride layer includes a third nitride concentration. And the third nitride concentration is larger than the first nitride concentration and the second nitride concentration.