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公开(公告)号：US12096704B2
公开(公告)日：2024-09-17
申请号：US18383473
申请日：2023-10-24
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yuan Zhou , Xian Feng Du , Guoan Du , Guohai Zhang
CPC classification number: H10N70/063 , H10N70/24 , H10N70/826 , H10N70/841
Abstract: A semiconductor memory device includes a substrate having a first interlayer dielectric layer thereon; a lower metal interconnect layer in the first interlayer dielectric layer; a conductive via disposed on the lower metal interconnect layer; a bottom electrode disposed on the conductive via; a dielectric data storage layer having variable resistance disposed on the bottom electrode; a top electrode disposed on the dielectric data storage layer; and a protective layer covering sidewalls of the top electrode, the dielectric data storage layer, and the bottom electrode. The protective layer includes an annular, upwardly protruding portion around a perimeter of the top electrode.
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Patent Agency Ranking
公开(公告)号：US10026745B1
公开(公告)日：2018-07-17
申请号：US15405324
申请日：2017-01-13
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Han Wang , Xian Feng Du
IPC: H01L27/11568 , H01L29/792 , H01L29/49
Abstract: A semiconductor memory cell structure includes a substrate, a tunnel dielectric layer formed on the substrate, a blocking dielectric layer formed on the substrate, a control gate formed on the blocking dielectric layer, and a tri-layered charge-trapping layer sandwiched between the tunnel dielectric layer and the blocking dielectric layer. Furthermore, the tri-layered charge-trapping layer includes a bottom nitride layer formed on the substrate, a top nitride layer formed on the bottom nitride layer, and a middle nitride layer sandwiched between the bottom nitride layer and the top nitride layer. The bottom nitride layer includes a first nitride concentration, the top nitride layer includes a second nitride concentration, and the middle nitride layer includes a third nitride concentration. And the third nitride concentration is larger than the first nitride concentration and the second nitride concentration.
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公开(公告)号：US11844291B2
公开(公告)日：2023-12-12
申请号：US17353757
申请日：2021-06-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yuan Zhou , Xian Feng Du , Guoan Du , Guohai Zhang
CPC classification number: H10N70/063 , H10N70/24 , H10N70/826 , H10N70/841
Abstract: A semiconductor memory device includes a substrate having a first interlayer dielectric layer thereon; a lower metal interconnect layer in the first interlayer dielectric layer; a conductive via disposed on the lower metal interconnect layer; a bottom electrode disposed on the conductive via; a dielectric data storage layer having variable resistance disposed on the bottom electrode; a top electrode disposed on the dielectric data storage layer; and a protective layer covering sidewalls of the top electrode, the dielectric data storage layer, and the bottom electrode. The protective layer includes an annular, upwardly protruding portion around a perimeter of the top electrode.
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公开(公告)号：US20220407006A1
公开(公告)日：2022-12-22
申请号：US17353757
申请日：2021-06-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： YUAN ZHOU , Xian Feng Du , GUOAN DU , GUOHAI ZHANG
IPC: H01L45/00
Abstract: A semiconductor memory device includes a substrate having a first interlayer dielectric layer thereon; a lower metal interconnect layer in the first interlayer dielectric layer; a conductive via disposed on the lower metal interconnect layer; a bottom electrode disposed on the conductive via; a dielectric data storage layer having variable resistance disposed on the bottom electrode; a top electrode disposed on the dielectric data storage layer; and a protective layer covering sidewalls of the top electrode, the dielectric data storage layer, and the bottom electrode. The protective layer includes an annular, upwardly protruding portion around a perimeter of the top electrode.
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公开(公告)号：US20240057486A1
公开(公告)日：2024-02-15
申请号：US18383473
申请日：2023-10-24
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： YUAN ZHOU , Xian Feng Du , GUOAN DU , GUOHAI ZHANG
CPC classification number: H10N70/063 , H10N70/24 , H10N70/826 , H10N70/841
Abstract: A semiconductor memory device includes a substrate having a first interlayer dielectric layer thereon; a lower metal interconnect layer in the first interlayer dielectric layer; a conductive via disposed on the lower metal interconnect layer; a bottom electrode disposed on the conductive via; a dielectric data storage layer having variable resistance disposed on the bottom electrode; a top electrode disposed on the dielectric data storage layer; and a protective layer covering sidewalls of the top electrode, the dielectric data storage layer, and the bottom electrode. The protective layer includes an annular, upwardly protruding portion around a perimeter of the top electrode.
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公开(公告)号：US20180204848A1
公开(公告)日：2018-07-19
申请号：US15405324
申请日：2017-01-13
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： HAN WANG , Xian Feng Du
IPC: H01L27/11568 , H01L29/792 , H01L29/49
CPC classification number: H01L27/11568 , H01L29/4916 , H01L29/792
Abstract: A semiconductor memory cell structure includes a substrate, a tunnel dielectric layer formed on the substrate, a blocking dielectric layer formed on the substrate, a control gate formed on the blocking dielectric layer, and a tri-layered charge-trapping layer sandwiched between the tunnel dielectric layer and the blocking dielectric layer. Furthermore, the tri-layered charge-trapping layer includes a bottom nitride layer formed on the substrate, a top nitride layer formed on the bottom nitride layer, and a middle nitride layer sandwiched between the bottom nitride layer and the top nitride layer. The bottom nitride layer includes a first nitride concentration, the top nitride layer includes a second nitride concentration, and the middle nitride layer includes a third nitride concentration. And the third nitride concentration is larger than the first nitride concentration and the second nitride concentration.
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