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    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    2.
    发明公开
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20230223306A1

    公开(公告)日：2023-07-13

    申请号：US17672638

    申请日：2022-02-15

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ta-Wei Chiu ,  Ping-Hung Chiang ,  Chia-Wen Lu ,  Chia-Ling Wang ,  Wei-Lun Huang

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/762

    CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L27/088

    Abstract: Semiconductor device and method of fabricating the same, the semiconductor device includes a substrate, a first transistor, a second transistor, a third transistor, and a plurality of shallow trench isolations. The first transistor is disposed in a medium-voltage region and includes a first plane, a first gate dielectric layer, and a first gate electrode. The second transistor is disposed in a boundary region and includes a second plane, a second gate dielectric layer, and a second gate electrode. The third transistor is disposed in a lower-voltage region and includes a third plane, a third gate dielectric layer, and a third gate electrode. The shallow trench isolations are disposed in the substrate, wherein top surfaces of the shallow trench isolations in the medium-voltage region, the boundary region and the low-voltage region are coplanar with top surfaces of the first gate dielectric layer and the second gate dielectric layer.

    Semiconductor device and method of fabricating the same
    4.
    发明授权
    Semiconductor device and method of fabricating the same 有权

    公开(公告)号：US12100624B2

    公开(公告)日：2024-09-24

    申请号：US17672638

    申请日：2022-02-15

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ta-Wei Chiu ,  Ping-Hung Chiang ,  Chia-Wen Lu ,  Chia-Ling Wang ,  Wei-Lun Huang

    IPC: H01L21/8234 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423

    CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L27/088

    Abstract: Semiconductor device and method of fabricating the same, the semiconductor device includes a substrate, a first transistor, a second transistor, a third transistor, and a plurality of shallow trench isolations. The first transistor is disposed in a medium-voltage region and includes a first plane, a first gate dielectric layer, and a first gate electrode. The second transistor is disposed in a boundary region and includes a second plane, a second gate dielectric layer, and a second gate electrode. The third transistor is disposed in a lower-voltage region and includes a third plane, a third gate dielectric layer, and a third gate electrode. The shallow trench isolations are disposed in the substrate, wherein top surfaces of the shallow trench isolations in the medium-voltage region, the boundary region and the low-voltage region are coplanar with top surfaces of the first gate dielectric layer and the second gate dielectric layer.

    SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
    6.
    发明公开
    SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF 审中-公开

    公开(公告)号：US20240243004A1

    公开(公告)日：2024-07-18

    申请号：US18109225

    申请日：2023-02-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chia-Ling Wang ,  Ping-Hung Chiang ,  Ta-Wei Chiu ,  Chia-Wen Lu ,  Wei-Lun Huang ,  Yueh-Chang Lin

    IPC: H01L21/762 ,  H01L23/13

    CPC classification number: H01L21/76224 ,  H01L23/13

    Abstract: A semiconductor structure includes a substrate having a first device region and a second device region in proximity to the first device region. A first trench isolation structure is disposed in the substrate between the first device region and the second device region. The first trench isolation structure includes a first bottom surface within the first device region and a second bottom surface within the second device region. The first bottom surface is lower than the second bottom surface. The first trench isolation structure includes a first top surface within the first device region and a second top surface within the second device region. The first top surface is coplanar with the second top surface.

    Semiconductor structure and forming method thereof
    7.
    发明申请
    Semiconductor structure and forming method thereof 有权

    公开(公告)号：US20230080968A1

    公开(公告)日：2023-03-16

    申请号：US17495783

    申请日：2021-10-06

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei-Lun Huang ,  Chia-Ling Wang ,  Chia-Wen Lu ,  Ping-Hung Chiang

    IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234

    Abstract: The invention provides a method for forming a semiconductor structure, which comprises providing a substrate, sequentially a first groove and a second groove are formed in the substrate, the depth of the first groove is different from the depth of the second groove, a first oxide layer is formed in the first groove, a second oxide layer is formed in the second groove, an etching step is performed to remove part of the first oxide layer, a first gate structure is formed on the first oxide layer, and a second gate structure is formed on the second oxide layer.

    Manufacturing method of semiconductor device
    8.
    发明授权
    Manufacturing method of semiconductor device 有权

    公开(公告)号：US12183809B2

    公开(公告)日：2024-12-31

    申请号：US17673819

    申请日：2022-02-17

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei-Lun Huang ,  Chia-Ling Wang ,  Chia-Wen Lu ,  Ta-Wei Chiu ,  Ping-Hung Chiang

    IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/423

    Abstract: A manufacturing method of a semiconductor device includes the following steps. A first recess and a second recess are formed in a first region and a second region of a semiconductor substrate, respectively. A bottom surface of the first recess is lower than a bottom surface of the second recess in a vertical direction. A first gate oxide layer and a second gate oxide layer are formed concurrently. At least a portion of the first gate oxide layer is formed in the first recess, and at least a portion of the second gate oxide layer is formed in the second recess. A removing process is performed for removing a part of the second gate oxide layer. A thickness of the second gate oxide layer is less than a thickness of the first gate oxide layer after the removing process.

    MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
    9.
    发明公开
    MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230231035A1

    公开(公告)日：2023-07-20

    申请号：US17673819

    申请日：2022-02-17

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wei-Lun Huang ,  Chia-Ling Wang ,  Chia-Wen Lu ,  Ta-Wei Chiu ,  Ping-Hung Chiang

    IPC: H01L29/66 ,  H01L29/40 ,  H01L21/8234

    CPC classification number: H01L29/66704 ,  H01L29/401 ,  H01L21/823462 ,  H01L29/42364

    Abstract: A manufacturing method of a semiconductor device includes the following steps. A first recess and a second recess are formed in a first region and a second region of a semiconductor substrate, respectively. A bottom surface of the first recess is lower than a bottom surface of the second recess in a vertical direction. A first gate oxide layer and a second gate oxide layer are formed concurrently. At least a portion of the first gate oxide layer is formed in the first recess, and at least a portion of the second gate oxide layer is formed in the second recess. A removing process is performed for removing a part of the second gate oxide layer. A thickness of the second gate oxide layer is less than a thickness of the first gate oxide layer after the removing process.

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