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    Method for forming resistive random access memory structure
    1.
    发明授权
    Method for forming resistive random access memory structure 有权

    公开(公告)号：US12193345B2

    公开(公告)日：2025-01-07

    申请号：US18503140

    申请日：2023-11-06

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H10N70/20 ,  H10B63/00 ,  H10N70/00

    Abstract: A resistive random access memory (RRAM) structure includes a RRAM cell, spacers and a dielectric layer. The RRAM cell is disposed on a substrate. The spacers are disposed beside the RRAM cell, wherein widths of top surfaces of the spacers are larger than or equal to widths of bottom surfaces of the spacers. The dielectric layer blanketly covers the substrate and sandwiches the RRAM cell, wherein the spacers are located in the dielectric layer. A method for forming the resistive random access memory (RRAM) structure is also provided.

    SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME 有权

    公开(公告)号：US20220359618A1

    公开(公告)日：2022-11-10

    申请号：US17870814

    申请日：2022-07-21

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A semiconductor device includes a substrate having a memory region and a logic region. A first dielectric layer is disposed on the substrate. A first conductive structure and a second conductive structure are respectively formed in the first dielectric layer on the memory region and the logic region. A memory cell is formed on the first dielectric layer and directly contacts a top surface of the first conductive structure. A first cap layer continuously covers a top surface and a sidewall of the memory cell and directly contacts a top surface of the second conductive structure. A second dielectric layer is formed on the first cap layer. A third conductive structure penetrates through the second dielectric layer and the first cap layer to contact the memory cell.

    RESISTIVE RANDOM ACCESS MEMORY (RRAM) STRUCTURE AND FORMING METHOD THEREOF
    4.
    发明申请
    RESISTIVE RANDOM ACCESS MEMORY (RRAM) STRUCTURE AND FORMING METHOD THEREOF 有权

    公开(公告)号：US20220209112A1

    公开(公告)日：2022-06-30

    申请号：US17159160

    申请日：2021-01-27

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A resistive random access memory (RRAM) structure includes a RRAM cell, spacers and a dielectric layer. The RRAM cell is disposed on a substrate. The spacers are disposed beside the RRAM cell, wherein widths of top surfaces of the spacers are larger than or equal to widths of bottom surfaces of the spacers. The dielectric layer blanketly covers the substrate and sandwiches the RRAM cell, wherein the spacers are located in the dielectric layer. A method for forming said resistive random access memory (RRAM) structure is also provided.

    Resistive random access memory structure and method for manufacturing the same
    6.
    发明授权
    Resistive random access memory structure and method for manufacturing the same 有权

    公开(公告)号：US11094880B2

    公开(公告)日：2021-08-17

    申请号：US16504491

    申请日：2019-07-08

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A resistive random access memory structure includes a bottom electrode; a variable resistance layer disposed on the bottom electrode; a top electrode disposed on the variable resistance layer; a protection layer surrounding the variable resistance layer, wherein a top surface of the protection layer and a top surface of the top electrode are coplanar; and an upper interconnect structure disposed on the top electrode, wherein the upper interconnect structure is electrically connected to the top electrode and directly contacts a sidewall of the protection layer.

    Semiconductor memory device and fabrication method thereof
    7.
    发明授权
    Semiconductor memory device and fabrication method thereof 有权

    公开(公告)号：US10608006B2

    公开(公告)日：2020-03-31

    申请号：US16038197

    申请日：2018-07-18

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H01L27/115 ,  H01L27/11568 ,  H01L29/792 ,  H01L21/28

    Abstract: A semiconductor memory device includes a memory gate disposed on a main surface of a substrate. The memory has a first sidewall and a second sidewall opposite to the first sidewall. A control gate is in proximity to the memory gate. The control gate has a third sidewall directly facing the second sidewall, and a fourth sidewall opposite to the third sidewall. A gap is provided between the second sidewall of the memory gate and the third sidewall of the control gate. A first single spacer structure is disposed on the first sidewall of the memory gate. A second single spacer structure is disposed on the fourth sidewall of the control gate. A gap-filling layer is deposited into the gap and fills up the gap.

    SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF 审中-公开

    公开(公告)号：US20200013793A1

    公开(公告)日：2020-01-09

    申请号：US16038197

    申请日：2018-07-18

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

    IPC: H01L27/11568 ,  H01L21/28 ,  H01L29/792

    Abstract: A semiconductor memory device includes a memory gate disposed on a main surface of a substrate. The memory has a first sidewall and a second sidewall opposite to the first sidewall. A control gate is in proximity to the memory gate. The control gate has a third sidewall directly facing the second sidewall, and a fourth sidewall opposite to the third sidewall. A gap is provided between the second sidewall of the memory gate and the third sidewall of the control gate. A first single spacer structure is disposed on the first sidewall of the memory gate. A second single spacer structure is disposed on the fourth sidewall of the control gate. A gap-filling layer is deposited into the gap and fills up the gap.

    RESISTIVE MEMORY DEVICE
    9.
    发明公开
    RESISTIVE MEMORY DEVICE 审中-公开

    公开(公告)号：US20240188306A1

    公开(公告)日：2024-06-06

    申请号：US18096532

    申请日：2023-01-12

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jen Wang ,  Yu-Huan Yeh ,  Chuan-Fu Wang ,  Hsiang-Hung Peng

    IPC: H10B63/00

    CPC classification number: H10B63/82

    Abstract: A resistive memory device includes a dielectric layer, a first via connection structure, a first stacked structure, and a first insulating structure. The first via connection structure is disposed in the dielectric layer. The first stacked structure is disposed on the first via connection structure and the dielectric layer. The first insulating structure penetrates through a portion of the first stacked structure in a vertical direction and divides the first stacked structure into a first cell unit and a second cell unit. The first cell unit and the second cell unit include a first shared bottom electrode, and the first insulating structure is disposed directly on the first shared bottom electrode.

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