公开(公告)号：US20180358475A1

公开(公告)日：2018-12-13

申请号：US15655847

申请日：2017-07-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： PENGFEI GUO ,  Shao-Hui Wu ,  HAI BIAO YAO ,  Yu-Cheng Tung ,  Yuanli Ding ,  ZHIBIAO ZHOU

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/49 ,  H01L29/417

CPC classification number: H01L29/78696 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/78391 ,  H01L29/78648 ,  H01L29/7869

Abstract: A semiconductor device includes a substrate, a source region and a drain region, a gate dielectric layer, and a ferroelectric material layer. The ferroelectric material layer overlaps with the source region and overlaps with the drain region. The substrate further comprises a channel layer. A gate electrode is disposed on the substrate. The ferroelectric material layer is disposed between the channel layer and the gate electrode.

公开(公告)号：US10354711B2

公开(公告)日：2019-07-16

申请号：US15691729

申请日：2017-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yuanli Ding ,  Zhibiao Zhou

IPC: G11C11/22 ,  H01L29/786 ,  H01L29/49

Abstract: A dual mode memory system is provided in the present invention, which includes a memory cell array with a plurality of oxide-semiconductor field effect transistors, each said oxide-semiconductor field effect transistor has a ferroelectric layer in the bottom gate to modulate the bottom gate bias voltage according to the polarization voltages provided by the dual mode control unit.

公开(公告)号：US20190066750A1

公开(公告)日：2019-02-28

申请号：US15691729

申请日：2017-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yuanli Ding ,  ZHIBIAO ZHOU

IPC: G11C11/22 ,  H01L29/786 ,  H01L29/49

CPC classification number: G11C11/221 ,  G11C5/146 ,  G11C11/223 ,  G11C11/2297 ,  H01L29/4908 ,  H01L29/78648 ,  H01L29/7869

Abstract: A dual mode memory system is provided in the present invention, which includes a memory cell array with a plurality of oxide-semiconductor field effect transistors, each said oxide-semiconductor field effect transistor has a ferroelectric layer in the bottom gate to modulate the bottom gate bias voltage according to the polarization voltages provided by the dual mode control unit.

公开(公告)号：US20190279701A1

公开(公告)日：2019-09-12

申请号：US16424485

申请日：2019-05-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yuanli Ding ,  ZHIBIAO ZHOU

IPC: G11C11/22 ,  H01L29/49 ,  H01L29/786

Abstract: A dual mode memory system is provided in the present invention, which includes a memory cell array with a plurality of oxide-semiconductor field effect transistors, each said oxide-semiconductor field effect transistor has a ferroelectric layer in the bottom gate to modulate the bottom gate bias voltage according to the polarization voltages provided by the dual mode control unit.

公开(公告)号：US10410708B1

公开(公告)日：2019-09-10

申请号：US16424485

申请日：2019-05-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yuanli Ding ,  Zhibiao Zhou

IPC: G11C11/22 ,  H01L29/786 ,  H01L29/49

Abstract: A dual mode memory system is provided in the present invention, which includes a memory cell array with a plurality of oxide-semiconductor field effect transistors, each said oxide-semiconductor field effect transistor has a ferroelectric layer in the bottom gate to modulate the bottom gate bias voltage according to the polarization voltages provided by the dual mode control unit.