公开(公告)号：US20210348684A1

公开(公告)日：2021-11-11

申请号：US16889816

申请日：2020-06-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： HAI BIAO YAO ,  Su Xing ,  JINYU LIAO ,  Purakh Raj Verma

IPC: F16J15/06 ,  H05K1/02 ,  H05K1/18 ,  H05K9/00

Abstract: The invention provides a seal ring structure, which comprises a substrate, and a seal ring positioned on the substrate, wherein the seal ring comprises an inner seal ring comprising a plurality of inner seal units, wherein each of the inner seal units is arranged at intervals with each other, an outer seal ring comprising a plurality of outer seal units arranged at the periphery of the inner seal ring, wherein each of the outer seal units is arranged at intervals with each other, and a plurality of groups of fence-shaped seal units, wherein at least one group of fence-shaped seal units is positioned between one of the inner seal units and the other adjacent outer seal unit.

公开(公告)号：US20170084614A1

公开(公告)日：2017-03-23

申请号：US14856565

申请日：2015-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shao-Hui Wu ,  ZHIBIAO ZHOU ,  HAI BIAO YAO ,  Chi-Fa Ku ,  Chen-Bin Lin

IPC: H01L27/108 ,  H01L29/786

CPC classification number: H01L27/10832 ,  H01L27/10867 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/7869

Abstract: A memory cell includes a substrate, a deep trench (DT) capacitor formed in the substrate, at least an insulting layer formed on the substrate, and an oxide semiconductor field effect transistor (OS FET) device formed on the insulating layer. And more important, the OS FET device is electrically connected to the DT capacitor.

公开(公告)号：US20190109199A1

公开(公告)日：2019-04-11

申请号：US15725288

申请日：2017-10-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： HAI BIAO YAO ,  Shao-Hui Wu ,  Xiang Li ,  HSIAO YU CHIA ,  Yu-Cheng Tung

IPC: H01L29/49 ,  H01L21/225 ,  H01L21/02 ,  H01L29/786 ,  H01L29/04

Abstract: An oxide semiconductor device includes an oxide semiconductor channel layer, a first gate dielectric layer, a first gate electrode, a source electrode, and a drain electrode. The oxide semiconductor channel layer includes a channel region. The first gate dielectric layer is disposed on the oxide semiconductor channel layer. The first gate electrode is disposed on the first gate dielectric layer. The source electrode and the drain electrode are disposed at two opposite sides of the first gate electrode in a first direction respectively. The first gate electrode includes a metal material with a work function higher than 4.7 electron volts (eV). A thickness of the oxide semiconductor channel layer is smaller than one third of a length of the channel region in the first direction.

公开(公告)号：US20180358475A1

公开(公告)日：2018-12-13

申请号：US15655847

申请日：2017-07-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： PENGFEI GUO ,  Shao-Hui Wu ,  HAI BIAO YAO ,  Yu-Cheng Tung ,  Yuanli Ding ,  ZHIBIAO ZHOU

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/49 ,  H01L29/417

CPC classification number: H01L29/78696 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/78391 ,  H01L29/78648 ,  H01L29/7869

Abstract: A semiconductor device includes a substrate, a source region and a drain region, a gate dielectric layer, and a ferroelectric material layer. The ferroelectric material layer overlaps with the source region and overlaps with the drain region. The substrate further comprises a channel layer. A gate electrode is disposed on the substrate. The ferroelectric material layer is disposed between the channel layer and the gate electrode.

公开(公告)号：US20210210605A1

公开(公告)日：2021-07-08

申请号：US17191720

申请日：2021-03-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： HAI BIAO YAO ,  Su Xing

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/36 ,  H01L29/66

Abstract: An SOI semiconductor device includes a substrate, a buried oxide layer disposed on the substrate, a top semiconductor layer disposed on the buried oxide layer, a source doping region and a drain doping region in the top semiconductor layer, a channel region between the source doping region and the drain doping region in the top semiconductor layer, a gate electrode on the channel region, and an embedded doping region disposed in the top semiconductor layer and directly under the channel region. The embedded doping region acts as a hole sink to alleviate or avoid floating body effects.

公开(公告)号：US20180033891A1

公开(公告)日：2018-02-01

申请号：US15253908

申请日：2016-09-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： XIAODONG PU ,  Shao-Hui Wu ,  HAI BIAO YAO ,  Qinggang Xing ,  Chien-Ming Lai ,  Jun Zhu ,  Yu-Cheng Tung ,  ZHIBIAO ZHOU

IPC: H01L29/786 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/1248 ,  H01L29/41725 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/78648

Abstract: An oxide semiconductor device includes an oxide semiconductor transistor and a protection wall. The protection wall extends in a vertical direction and surrounds the oxide semiconductor transistor. The oxide semiconductor transistor includes a first oxide semiconductor layer, and a bottom surface of the protection wall is lower than the first oxide semiconductor layer in the vertical direction. In the oxide semiconductor device of the present invention, the protection wall is used to surround the oxide semiconductor transistor for improving the ability of blocking environment substances from entering the oxide semiconductor transistor. The electrical stability and product reliability of the oxide semiconductor device are enhanced accordingly.