公开(公告)号：US20250169208A1

公开(公告)日：2025-05-22

申请号：US19032468

申请日：2025-01-21

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Hau-Yuan Huang ,  Chia-Chen Tsai ,  Jia-Bin Yeh ,  Shou-Wei Hsieh

IPC: H10F39/00

Abstract: Provided is a manufacturing method of an NMOS structure that includes a semiconductor substrate, a dielectric structure, a source/drain doped region, a channel region, a gate structure and two isolation P-type wells. The dielectric structure is formed in the semiconductor substrate to define an active region, in which the source/drain doped region and the channel region are formed. The channel region includes two opposite first sides and two opposite second sides. The source/drain doped region is respectively formed between the two second sides and the dielectric structure. The gate structure is formed on the semiconductor substrate. The gate structure covers a part of the dielectric structure beside the first sides. The two isolation P-type wells are formed in a part of the dielectric structure not covered by the gate structure. The isolation P-type wells respectively surround a periphery of the source/drain doped region and end at the respective second side.

公开(公告)号：US12237350B2

公开(公告)日：2025-02-25

申请号：US17539222

申请日：2021-12-01

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Hau-Yuan Huang ,  Chia-Chen Tsai ,  Jia-Bin Yeh ,  Shou-Wei Hsieh

IPC: H01L27/146

Abstract: An NMOS structure includes a semiconductor substrate, a dielectric structure, a source doped region, a drain doped region, a channel region, a gate structure and two isolation P-type wells. The dielectric structure is formed in the semiconductor substrate to define an active region, in which the source/drain doped region and the channel region are formed. The channel region includes two opposite first sides and two opposite second sides. The source/drain doped region is respectively formed between the two second sides and the dielectric structure. The gate structure is formed on the semiconductor substrate. The gate structure covers a part of the dielectric structure beside the first sides. The two isolation P-type wells are formed in a part of the dielectric structure not covered by the gate structure. The isolation P-type wells respectively surround a periphery of the source/drain doped region and end at the respective second side.

公开(公告)号：US20230145660A1

公开(公告)日：2023-05-11

申请号：US17539222

申请日：2021-12-01

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Hau-Yuan Huang ,  Chia-Chen Tsai ,  Jia-Bin Yeh ,  Shou-Wei Hsieh

IPC: H01L27/146

CPC classification number: H01L27/14612 ,  H01L27/14689

Abstract: An NMOS structure includes a semiconductor substrate, a dielectric structure, a source doped region, a drain doped region, a channel region, a gate structure and two isolation P-type wells. The dielectric structure is formed in the semiconductor substrate to define an active region, in which the source/drain doped region and the channel region are formed. The channel region includes two opposite first sides and two opposite second sides. The source/drain doped region is respectively formed between the two second sides and the dielectric structure. The gate structure is formed on the semiconductor substrate. The gate structure covers a part of the dielectric structure beside the first sides. The two isolation P-type wells are formed in a part of the dielectric structure not covered by the gate structure. The isolation P-type wells respectively surround a periphery of the source/drain doped region and end at the respective second side.