公开(公告)号：US11869854B2

公开(公告)日：2024-01-09

申请号：US17159181

申请日：2021-01-27

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chien-Ming Lai ,  Hui-Ling Chen ,  Zhi-Rui Sheng

IPC: H01L23/64 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L23/645 ,  H01L23/5227 ,  H01L24/94 ,  H01L24/80 ,  H01L24/83 ,  H01L2224/32245 ,  H01L2224/48139

Abstract: A semiconductor structure in which the upper and lower semiconductor wafers are bonded by a hybrid bonding method is provided. The two semiconductor wafers each have discontinuous multiple metal traces or spiral coil-shaped metal traces. By hybrid bonding the two semiconductor wafers, multiple discontinuous metal traces are bonded together to form an inductance element with a continuous and non-intersecting path, or the two spiral coil-shaped metal traces are bonded together to form an inductance element. In this semiconductor structure, the inductance element formed by hybrid bonding has the advantage that the inductance value is easily adjusted.

公开(公告)号：US20230147512A1

公开(公告)日：2023-05-11

申请号：US17543757

申请日：2021-12-07

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： KUO-HSING LEE ,  Po-Wen Su ,  Chien-Liang Wu ,  Sheng-Yuan Hsueh

IPC: H01L27/112 ,  H01L49/02

CPC classification number: H01L27/11206 ,  H01L28/75 ,  H01L28/92

Abstract: An OTP memory capacitor structure includes a semiconductor substrate, a bottom electrode, a capacitor insulating layer and a metal electrode stack structure. The bottom electrode is provided on the semiconductor substrate. The capacitor insulating layer is provided on the bottom electrode. The metal electrode stack structure includes a metal layer, an insulating sacrificial layer and a capping layer stacked in sequence. The metal layer is provided on the capacitor insulating layer and is used as a top electrode. The insulating sacrificial layer is provided between the metal layer and the capping layer. A manufacturing method of the OTP memory capacitor structure is also provided. By the provision of the insulating sacrificial layer, the bottom electrode formed first can be prevented from being damaged by subsequent etching and other processes, so that the OTP memory capacitor structure has better electrical characteristics.

公开(公告)号：US20210036152A1

公开(公告)日：2021-02-04

申请号：US16530954

申请日：2019-08-02

Applicant: United Microelectronics Corporation

Inventor： Tsung-Hsun Tsai

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/45 ,  H01L21/02 ,  H01L21/3205

Abstract: A new method for fabricating a semiconductor device with high selection phosphoric acid solution and eliminating the step of oxide removal and thus reducing oxide loss to improve yield gain and cost saving.

公开(公告)号：US10903179B2

公开(公告)日：2021-01-26

申请号：US16294906

申请日：2019-03-06

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Yu-Jie Lin

IPC: H01L23/00

Abstract: Semiconductor apparatus and method for manufacturing semiconductor apparatus are provided. Semiconductor apparatus includes a semiconductor substrate having metal pads, a first passivation layer, a second passivation layer, an under bump metal layer, a stress buffer layer, a copper pillar and a solder structure. First passivation layer is formed on the semiconductor substrate and covers a portion of each metal pad, the first passivation layer has first passivation layer openings to expose a first portion of each metal pad. Second passivation layer is formed on the first passivation layer, the second passivation layer has second passivation layer openings to expose a second portion of each metal pad. Under bump metal layer is formed on the second portion of each metal pad exposed by the second passivation layer opening. Stress buffer layer is formed on the under bump metal layer, and the copper pillar is disposed on the stress buffer layer.

公开(公告)号：US10475640B2

公开(公告)日：2019-11-12

申请号：US16137583

申请日：2018-09-21

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Yan-Da Chen ,  Weng Yi Chen ,  Chang-Sheng Hsu ,  Kuan-Yu Wang ,  Yuan Sheng Lin

IPC: H01L21/02 ,  B81C1/00 ,  H01L23/31 ,  H01L21/768

Abstract: Provided herein is a method for manufacturing a semiconductor device. A substrate including a MEMS region and a connection region thereon is provided; a dielectric layer disposed on the substrate in the connection region is provided; a poly-silicon layer disposed on the dielectric layer is provided, wherein the poly-silicon layer serves as an etch-stop layer; a connection pad disposed on the poly-silicon layer is provided; and a passivation layer covering the dielectric layer is provided, wherein the passivation layer includes an opening that exposes the connection pad and a transition region between the connection pad and the passivation layer, and a conductive layer conformally covering the connection pad and the poly-silicon layer in the transition region is provided.

公开(公告)号：US10332978B2

公开(公告)日：2019-06-25

申请号：US15689780

申请日：2017-08-29

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chia-Lin Lu ,  Yu-Cheng Tung ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang

IPC: H01L29/66 ,  H01L29/78 ,  H01L23/485 ,  H01L21/768

Abstract: A semiconductor device with reinforced gate spacers and a method of fabricating the same. The semiconductor device includes low-k dielectric gate spacers adjacent to a gate structure. A high-k dielectric material is disposed over an upper surface of the low-k dielectric gate spacers to prevent unnecessary contact between the gate structure and a self-aligned contact structure. The high-k dielectric material may be disposed, if desired, over an upper surface of the gate structure to provide additional isolation of the gate structure from the self-aligned contact structure.

公开(公告)号：US20190027358A1

公开(公告)日：2019-01-24

申请号：US16137583

申请日：2018-09-21

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： YAN-DA CHEN ,  WENG YI CHEN ,  CHANG-SHENG HSU ,  KUAN-YU WANG ,  YUAN SHENG LIN

IPC: H01L21/02 ,  B81C1/00

Abstract: Provided herein is a method for manufacturing a semiconductor device. A substrate including a MEMS region and a connection region thereon is provided; a dielectric layer disposed on the substrate in the connection region is provided; a poly-silicon layer disposed on the dielectric layer is provided, wherein the poly-silicon layer serves as an etch-stop layer; a connection pad disposed on the poly-silicon layer is provided; and a passivation layer covering the dielectric layer is provided, wherein the passivation layer includes an opening that exposes the connection pad and a transition region between the connection pad and the passivation layer, and a conductive layer conformally covering the connection pad and the poly-silicon layer in the transition region is provided.

公开(公告)号：US20180306738A1

公开(公告)日：2018-10-25

申请号：US15493120

申请日：2017-04-20

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Chia-Wei LEE ,  Chang-Sheng HSU ,  Chih-Fan HU ,  Chin-Jen CHENG ,  Chang Hsin WU

IPC: G01N27/12

CPC classification number: G01N27/128

Abstract: The present invention provides a structure of a gas sensor, comprising: a support, having a front side, a back side opposite to the front side, a cell region, and a peripheral region circling the cell region; a cavity, formed on the back side of the support in the cell region; a heater, disposed on the front side of the support covering the cavity; a sensing element, disposed on the heater; and a sealing layer, formed on the back side of the support covering inside the cavity.

公开(公告)号：US10103248B2

公开(公告)日：2018-10-16

申请号：US15452734

申请日：2017-03-08

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Tai-Ju Chen ,  Yi-Han Ye ,  Te-Chih Chen

IPC: H01L27/148 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L29/40 ,  H01L29/08 ,  H01L29/165 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51

Abstract: A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The method includes: providing a substrate with a fin structure to define a first and a second type well regions; forming a trench in the first-type well region to separate the fin structure into a first part and a second part; forming a STI structure in the trench; forming a first and a second polycrystalline silicon gate stack structures at the fin structure; forming discontinuous openings on the exposed fin structure and growing an epitaxial material layer in the openings; doping the epitaxial material layer to form a drain and a source doped layers in the first and second parts respectively; and performing a RMG process to replace the first and second polycrystalline silicon gate stack structures with a first and second metal gate stack structures respectively.

公开(公告)号：US09978854B2

公开(公告)日：2018-05-22

申请号：US15156351

申请日：2016-05-17

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Jhen-Cyuan Li ,  Shui-Yen Lu ,  Man-Ling Lu ,  Yu-Cheng Tung ,  Chung-Fu Chang

IPC: H01L29/66 ,  H01L29/161 ,  H01L21/30 ,  H01L21/82 ,  H01L27/088 ,  H01L29/78 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/823425 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/7848

Abstract: An etching method adapted to forming grooves in Si-substrate and FinFET transistor manufactured thereof are provided. The etching method includes providing a silicon substrate, at least two gate structures formed on the silicon substrate and at least two gate spacer structures disposed on the silicon substrate; performing a first etching process on the silicon substrate to form a first groove, which has a base and two inclined sidewalls, ascending to respective bottoms of the gate structures, and are interconnected with the base, respectively; and performing a second etching process on the silicon substrate at the base of the first groove, so as to form a second groove in a trench shape, wherein the two inclined sidewalls of the first groove are interconnected with the second groove respectively, and the first etching process is substantially different from the second etching process.