公开(公告)号：US20230343373A1

公开(公告)日：2023-10-26

申请号：US18306531

申请日：2023-04-25

Applicant: UNIVERSITY OF VIRGINIA PATENT FOUNDATION

Inventor： KEVIN SKADRON ,  MARZIEH LENJANI

IPC: G11C7/10 ,  G06F17/16

CPC classification number: G11C7/1039 ,  G11C7/1057 ,  G06F17/16

Abstract: An integrated circuit memory device can include a plurality of banks of memory, each of the banks of memory including a first pair of sub-arrays comprising first and second sub-arrays, the first pair of sub-arrays configured to store data in memory cells of the first pair of sub-arrays, a first row buffer memory circuit located in the integrated circuit memory device adjacent to the first pair of sub-arrays and configured to store first row data received from the first pair of sub-arrays and configured to transfer the row data into and/or out of the first row buffer memory circuit, and a first sub-array level processor circuit in the integrated circuit memory device adjacent to the first pair of sub-arrays and operatively coupled to the first row data, wherein the first sub-array level processor circuit is configured to perform column oriented processing a sparse matrix kernel stored, at least in-part, in the first pair of sub-arrays, with input vector values stored, at least in part, in the first pair of sub-arrays to provide output vector values representing products of values stored in columns of the sparse matrix kernel with the input vector values.