公开(公告)号：US09341884B2

公开(公告)日：2016-05-17

申请号：US14034396

申请日：2013-09-23

Applicant: United Microelectronics Corp.

Inventor： Yi-Ming Hsu ,  Feng-Ying Hsu ,  Chieh-Yu Tsai

IPC: G02F1/1335 ,  G02F1/1343 ,  G02F1/1362 ,  G02B5/08

CPC classification number: G02F1/133553 ,  G02B5/0816 ,  G02B5/0875 ,  G02F1/134336 ,  G02F1/136277

Abstract: The present invention provides a LCOS device including a silicon substrate, a first dielectric layer, a first mirror layer, a second dielectric layer, and a second mirror layer. The first dielectric layer is disposed on the silicon substrate. The first mirror layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the first mirror layer. The second mirror layer is disposed on the second dielectric layer.

Abstract translation: 本发明提供一种包括硅衬底，第一介电层，第一镜层，第二介电层和第二镜层的LCOS器件。 第一电介质层设置在硅衬底上。 第一镜层设置在第一电介质层上。 第二介电层设置在第一镜层上。 第二镜层设置在第二介质层上。

公开(公告)号：US10373966B2

公开(公告)日：2019-08-06

申请号：US15264423

申请日：2016-09-13

Applicant: United Microelectronics Corp.

Inventor： Po-Han Jen ,  Chieh-Yu Tsai ,  Chun-Cheng Chiang

IPC: H01L27/112 ,  H01L49/02 ,  H01L21/28

Abstract: A Mask ROM is shown, including first resistors as a first part of memory cells, second resistors as a second part of memory cells, and contact plugs. Each first resistor includes: an undoped first poly-Si layer including an upper horizontal bar, a lower horizontal bar contiguous with the upper horizontal bar, and a step structure with a step height at which the two bars are contiguous, a spacer on the sidewall of the step structure, and a first silicide layer on the first poly-Si layer and being divided apart by the spacer. Each second resistor includes an undoped second poly-Si layer, and a contiguous second silicide layer on the second poly-Si layer. The contact plugs are disposed on the first silicide layer on the upper horizontal bar of each first poly-Si layer, and on the second silicide layer.

公开(公告)号：US20180076207A1

公开(公告)日：2018-03-15

申请号：US15264423

申请日：2016-09-13

Applicant: United Microelectronics Corp.

Inventor： Po-Han Jen ,  Chieh-Yu Tsai ,  Chun-Cheng Chiang

IPC: H01L27/112 ,  H01L49/02 ,  H01L29/06 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L27/11253 ,  H01L28/20

Abstract: A Mask ROM is shown, including first resistors as a first part of memory cells, second resistors as a second part of memory cells, and contact plugs. Each first resistor includes: an undoped first poly-Si layer including a convex portion and a step structure with a step height adjacent to the convex portion, a spacer on the sidewall of the step structure, and a first silicide layer on the first poly-Si layer and being divided apart by the spacer. Each second resistor includes an undoped second poly-Si layer, and a contiguous second silicide layer on the second poly-Si layer. The contact plugs are disposed on the first silicide layer on the convex portion of each first poly-Si layer, and on the second silicide layer.

公开(公告)号：US20150085234A1

公开(公告)日：2015-03-26

申请号：US14034396

申请日：2013-09-23

Applicant: United Microelectronics Corp.

Inventor： Yi-Ming Hsu ,  Feng-Ying Hsu ,  Chieh-Yu Tsai

IPC: G02F1/1335

CPC classification number: G02F1/133553 ,  G02B5/0816 ,  G02B5/0875 ,  G02F1/134336 ,  G02F1/136277

Abstract: The present invention provides a LCOS device including a silicon substrate, a first dielectric layer, a first mirror layer, a second dielectric layer, and a second mirror layer. The first dielectric layer is disposed on the silicon substrate. The first mirror layer is disposed on the first dielectric layer. The second dielectric layer is disposed on the first mirror layer. The second minor layer is disposed on the second dielectric layer.

Abstract translation: 本发明提供一种包括硅衬底，第一介电层，第一镜层，第二介电层和第二镜层的LCOS器件。 第一电介质层设置在硅衬底上。 第一镜层设置在第一电介质层上。 第二介电层设置在第一镜层上。 第二次要层设置在第二电介质层上。