公开(公告)号：US11417412B1

公开(公告)日：2022-08-16

申请号：US17189094

申请日：2021-03-01

Applicant: United Microelectronics Corp.

Inventor： Chung-Hao Chen ,  Hsiao-Hua Lu

IPC: G11C29/00 ,  G11C29/50 ,  G11C13/00

Abstract: A cell trace circuit includes a memory cell, a voltage generator and a measuring circuit. The memory cell has a resistor and a memory layer coupled in series to have a top electrode, a middle electrode and a bottom electrode, wherein the resistor and the memory layer are coupled at the middle electrode. The voltage generator provides a test bias to the memory cell ranging from a negative voltage to a positive voltage in a reset path or ranging from the positive voltage to the negative voltage in a set path. The measuring circuit is to determine a current (I) and a voltage (V) crossing the memory layer by the test bias.

公开(公告)号：US11294577B2

公开(公告)日：2022-04-05

申请号：US16831716

申请日：2020-03-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiao-Hua Lu ,  Hsin-Pang Lu

IPC: G06F3/06 ,  G06F11/08 ,  G06F16/22

Abstract: A non-volatile memory includes a plurality of data storage units arranged in an array, a plurality of redundant data storage units arranged in at least one row and a plurality of redundant address storage units arranged in at least one row. A storage size of each of the data storage units is word. Each of the data storage units is addressable by a row address and a column address. One of the redundant data storage units in a first column is configured to substitute for one of the data storage units in a second column. One of the redundant address storage units in a third column is configured to record the row address representative of the substituted one of the data storage units.

公开(公告)号：US20210263656A1

公开(公告)日：2021-08-26

申请号：US16831716

申请日：2020-03-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiao-Hua Lu ,  Hsin-Pang Lu

IPC: G06F3/06 ,  G06F11/08 ,  G06F16/22

Abstract: A non-volatile memory includes a plurality of data storage units arranged in an array, a plurality of redundant data storage units arranged in at least one row and a plurality of redundant address storage units arranged in at least one row. A storage size of each of the data storage units is word. Each of the data storage units is addressable by a row address and a column address. One of the redundant data storage units in a first column is configured to substitute for one of the data storage units in a second column. One of the redundant address storage units in a third column is configured to record the row address representative of the substituted one of the data storage units.