公开(公告)号：US20250096000A1

公开(公告)日：2025-03-20

申请号：US18487141

申请日：2023-10-16

Applicant: United Microelectronics Corp.

Inventor： Kun-Ju Li ,  Hsin-Jung Liu ,  Jhih Yuan Chen ,  I-Ming Lai ,  Ang Chan ,  Wei Xin Gao ,  Hsiang Chi Chien ,  Hao-Che Hsu ,  Chau Chung Hou ,  Zong Sian Wu

IPC: H01L21/304 ,  H01L21/306 ,  H01L21/762

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first wafer is provided. The first wafer includes a first substrate and a first device layer. A second wafer is provided. The second wafer includes a second substrate and a second device layer. The second device layer is bonded to the first device layer. An edge trimming process is performed on the first wafer and the second wafer to expose a first upper surface of the first substrate and a second upper surface of the first substrate and to form a damaged region in the first substrate below the first upper surface and the second upper surface. The second upper surface is higher than the first upper surface. A first photoresist layer is formed. The first photoresist layer is located on the second wafer and the second upper surface and exposes the first upper surface and the damaged region. The damaged region is removed by using the first photoresist layer as a mask. The first photoresist layer is removed.