公开(公告)号：US11257711B1

公开(公告)日：2022-02-22

申请号：US17023391

申请日：2020-09-17

申请人： UNITED MICROELECTRONICS CORP.

发明人： Fu-Shou Tsai ,  Yang-Ju Lu ,  Yong-Yi Lin ,  Yu-Lung Shih ,  Ching-Yang Chuang ,  Ji-Min Lin ,  Kun-Ju Li

IPC分类号： H01L21/768 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/02

摘要： A fabricating method of transistors includes providing a substrate with numerous transistors thereon. Each of the transistors includes a gate structure. A gap is disposed between gate structures adjacent to each other. Later, a protective layer and a first dielectric layer are formed in sequence to cover the substrate and the transistors and to fill in the gap. Next, numerous buffering particles are formed to contact the first dielectric layer. The buffering particles do not contact each other. Subsequently, a second dielectric layer is formed to cover the buffering particles. After that, a first planarization process is performed to remove part of the first dielectric layer, part of the second dielectric layer and buffering particles by taking the protective layer as a stop layer, wherein a removing rate of the second dielectric layer is greater than a removing rate of the buffering particles during the first planarization process.

公开(公告)号：US20210151666A1

公开(公告)日：2021-05-20

申请号：US17141194

申请日：2021-01-04

申请人： UNITED MICROELECTRONICS CORP.

发明人： Hui-Lin Wang ,  Tai-Cheng Hou ,  Wei-Xin Gao ,  Fu-Yu Tsai ,  Chin-Yang Hsieh ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Bin-Siang Tsai ,  Kun-Ju Li ,  Chih-Yueh Li ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Yu-Tsung Lai ,  Wei-Hao Huang

IPC分类号： H01L43/08 ,  H01L21/768 ,  H01L43/02 ,  H01L21/762

摘要： A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.

公开(公告)号：US20200185597A1

公开(公告)日：2020-06-11

申请号：US16216969

申请日：2018-12-11

申请人： UNITED MICROELECTRONICS CORP.

发明人： Kun-Ju Li ,  Hsin-Jung Liu ,  I-Ming Tseng ,  Chau-Chung Hou ,  Yu-Lung Shih ,  Fu-Chun Hsiao ,  Hui-Lin Wang ,  Tzu-Hsiang Hung ,  Chih-Yueh Li ,  Ang Chan ,  Jing-Yin Jhang

IPC分类号： H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12

摘要： A memory device includes an insulation layer, a memory cell region and an alignment mark region are defined on the insulation layer, an interconnection structure disposed in the insulation layer, a dielectric layer disposed on the insulation layer and the interconnection structure, the dielectric layer is disposed within the memory cell region and the alignment mark region, a conductive via plug disposed on the interconnection structure within the memory cell region, the conductive via plug has a concave top surface, an alignment mark trench penetrating the dielectric layer within the alignment mark region, a bottom electrode disposed on the conductive via plug within the memory cell region and disposed in the alignment mark trench within the alignment mark region, and a magnetic tunnel junction (MTJ) structure disposed on the bottom electrode within the memory cell region and disposed in the alignment mark trench within the alignment mark region.

公开(公告)号：US10192826B2

公开(公告)日：2019-01-29

申请号：US15853978

申请日：2017-12-26

申请人： UNITED MICROELECTRONICS CORP.

发明人： Kun-Ju Li ,  Kuo-Chin Hung ,  Min-Chuan Tsai ,  Wei-Chuan Tsai ,  Yi-Han Liao ,  Chun-Tsen Lu ,  Fu-Shou Tsai ,  Li-Chieh Hsu

IPC分类号： H01L23/52 ,  H01L29/41 ,  H01L23/528 ,  H01L23/532 ,  H01L23/485 ,  H01L21/768 ,  H01L23/522 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

摘要： A layout structure including a conductive structure is provided. The layout structure includes a dielectric layer formed on a substrate and a conductive structure formed in the dielectric layer. And the conductive structure further includes a barrier layer, a metal layer formed within the barrier layer, and a high resistive layer sandwiched in between the barrier layer and the metal layer.

公开(公告)号：US10008581B2

公开(公告)日：2018-06-26

申请号：US14840041

申请日：2015-08-30

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chun-Tsen Lu ,  Chien-Ming Lai ,  Lu-Sheng Chou ,  Ya-Huei Tsai ,  Ching-Hsiang Chiu ,  Yu-Tung Hsiao ,  Chen-Ming Huang ,  Kun-Ju Li ,  Yu-Ping Wang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  C22C32/00 ,  H01L29/51 ,  H01L21/28 ,  B32B1/00

CPC分类号： H01L29/66545 ,  B32B1/00 ,  B32B18/00 ,  C22C32/0068 ,  H01L21/28088 ,  H01L29/4238 ,  H01L29/4966 ,  H01L29/511

摘要： A semiconductor device is disclosed. The semiconductor device includes a substrate and a gate structure on the substrate. The gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, in which the top portion being a nitrogen rich portion, and the middle portion and the bottom portion being titanium rich portions.

公开(公告)号：US09966263B1

公开(公告)日：2018-05-08

申请号：US15587228

申请日：2017-05-04

申请人： United Microelectronics Corp.

发明人： Kun-Ju Li ,  Li-Chieh Hsu ,  Yi-Han Liao ,  Chun-Tsen Lu ,  Chih-Hsun Lin ,  Hsin-Jung Liu

IPC分类号： H01L21/033

CPC分类号： H01L21/0338 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337

摘要： A method of fabricating fin structure is provided. A patterned catalyst layer and a patterned passivation layer extending along a first direction are formed on a substrate. The patterned passivation layer is located on the patterned catalyst layer. A carbon layer is formed on at least one side of the patterned catalyst layer and includes hollow carbon tubes arranged along the first direction. Each hollow carbon tube extends along a second direction. A removal process is performed to remove the top and a portion of the bottom of each hollow carbon tube closest to the substrate, so that remnants are left and serve as a mask layer. Two adjacent remnants form a stripe pattern extending along the second direction. The patterned passivation layer and the patterned catalyst layer are removed. The pattern of the mask layer is transferred to the substrate to form fin structures. The mask layer is removed.

公开(公告)号：US09905430B1

公开(公告)日：2018-02-27

申请号：US15245194

申请日：2016-08-24

申请人： UNITED MICROELECTRONICS CORP.

发明人： Fu-Shou Tsai ,  Yu-Ting Li ,  Li-Chieh Hsu ,  Yi-Liang Liu ,  Kun-Ju Li ,  Po-Cheng Huang ,  Chien-Nan Lin

IPC分类号： H01L21/84 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234

CPC分类号： H01L21/31055 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02227 ,  H01L21/02271 ,  H01L21/31111 ,  H01L21/823431

摘要： A method for forming a semiconductor structure includes following steps. A substrate is provided, and a semiconductor layer is formed on the substrate. Next, a SiN-rich pre-oxide layer is formed on the semiconductor layer. After forming the SiN-rich pre-oxide layer, an anneal treatment is performed to partially transfer the SiN-rich pre-oxide layer to form a SiN layer and a SiO layer. And the SiO layer is formed the on the SiN layer. Subsequently, a planarization process is performed to remove a portion of the SiO layer to expose the SiN layer.

公开(公告)号：US20180033633A1

公开(公告)日：2018-02-01

申请号：US15220365

申请日：2016-07-26

申请人： UNITED MICROELECTRONICS CORP.

发明人： Fu-Shou Tsai ,  Yu-Ting Li ,  Li-Chieh Hsu ,  Yi-Liang Liu ,  Kun-Ju Li ,  Po-Cheng Huang ,  Chien-Nan Lin

IPC分类号： H01L21/308 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/027

CPC分类号： H01L21/3081 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0273 ,  H01L21/302 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/31056 ,  H01L21/31058 ,  H01L21/3212

摘要： A method for planarizing a silicon layer includes providing a silicon layer having at least one recess therein. Next, a photoresist layer is formed to cover the silicon layer and fill up the recess. Then, the photoresist layer is hardened. After that, part of the photoresist layer is removed by taking a top surface of the silicon layer as a stop layer. Finally the photoresist layer and the silicon layer are etched back simultaneously to remove the photoresist layer entirely.

公开(公告)号：US20160351674A1

公开(公告)日：2016-12-01

申请号：US15232796

申请日：2016-08-09

申请人： UNITED MICROELECTRONICS CORP.

发明人： Kun-Ju Li ,  Po-Cheng Huang ,  Yu-Ting Li ,  Jen-Chieh Lin ,  Chih-Hsun Lin ,  Tzu-Hsiang Hung ,  Wu-Sian Sie ,  I-Lun Hung ,  Wen-Chin Lin ,  Chun-Tsen Lu

IPC分类号： H01L29/423 ,  H01L21/66 ,  H01L29/51 ,  H01L21/324 ,  H01L29/66 ,  H01L21/02 ,  H01L21/321

CPC分类号： H01L29/42364 ,  H01L21/02271 ,  H01L21/02354 ,  H01L21/02362 ,  H01L21/31051 ,  H01L21/3212 ,  H01L21/324 ,  H01L21/823437 ,  H01L22/12 ,  H01L22/20 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

摘要： A semiconductor process includes the following steps. A dielectric layer is formed on a substrate, where the dielectric layer has at least a dishing from a first top surface. A shrinkable layer is formed to cover the dielectric layer, where the shrinkable layer has a second top surface. A treatment process is performed to shrink a part of the shrinkable layer according to a topography of the second top surface, thereby flattening the second top surface. A semiconductor structure formed by said semiconductor process is also provided.

摘要翻译： 半导体工艺包括以下步骤。 电介质层形成在基板上，其中电介质层至少具有来自第一顶表面的凹陷。 形成可收缩层以覆盖电介质层，其中可收缩层具有第二顶表面。 执行处理过程以根据第二顶表面的形貌收缩可收缩层的一部分，从而使第二顶表面变平。 还提供了由所述半导体工艺形成的半导体结构。

公开(公告)号：US09502303B2

公开(公告)日：2016-11-22

申请号：US14682265

申请日：2015-04-09

申请人： UNITED MICROELECTRONICS CORP.

发明人： Kun-Ju Li ,  Kuo-Chin Hung ,  Po-Cheng Huang ,  Yu-Ting Li ,  Wu-Sian Sie ,  Chun-Tsen Lu ,  Wen-Chin Lin ,  Fu-Shou Tsai

IPC分类号： H01L21/768 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/285

CPC分类号： H01L21/823475 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/32133 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823871

摘要： A method for manufacturing a semiconductor device is provided. A substrate with an insulation formed thereon is provided, wherein the insulation has plural trenches, and the adjacent trenches are spaced apart from each other. A barrier layer is formed on an upper surface of the insulation and in sidewalls of the trenches, and the barrier layer comprises overhung portions corresponding to the trenches. A seed layer is formed on the barrier layer. Then, an upper portion of the seed layer formed on an upper surface of the barrier layer is removed. An upper portion of the barrier layer is removed for exposing the upper surface of the insulation. Afterwards, the conductors are deposited along the seed layer for filling up the trenches, wherein the top surfaces of the conductors are substantially aligned with the upper surface of the insulation.

摘要翻译： 提供一种制造半导体器件的方法。 提供其上形成有绝缘体的基板，其中绝缘体具有多个沟槽，并且相邻的沟槽彼此间隔开。 在绝缘体的上表面和沟槽的侧壁中形成阻挡层，并且阻挡层包括对应于沟槽的悬垂部分。 种子层形成在阻挡层上。 然后，除去形成在阻挡层的上表面上的种子层的上部。 去除阻挡层的上部以暴露绝缘体的上表面。 之后，导体沿种子层沉积以填充沟槽，其中导体的顶表面基本上与绝缘体的上表面对齐。