公开(公告)号：US20240347588A1

公开(公告)日：2024-10-17

申请号：US18196441

申请日：2023-05-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Hung Chen ,  Ssu-I Fu ,  Yu-Hsiang Lin ,  Po-Kuang Hsieh ,  Jia-He Lin ,  Sheng-Yao Huang

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/76229

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a high-voltage (HV) region and a medium-voltage (MV) region, forming a first trench on the HV region, forming a second trench adjacent to the first trench and extending the first trench to form a third trench, forming a first shallow trench isolation (STI) in the second trench and a second STI in the third trench, and then forming a first gate structure between the first STI and the second STI. Preferably, a bottom surface of the second STI is lower than a bottom surface of the first STI.

公开(公告)号：US20250056859A1

公开(公告)日：2025-02-13

申请号：US18928226

申请日：2024-10-28

Applicant: United Microelectronics Corp.

Inventor： Jia-He Lin ,  Yu-Ruei Chen ,  Yu-Hsiang Lin

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor device includes a substrate, a plurality of planar transistors, a fin-type field effect transistor and a first nonactive structure. The substrate includes a first region and a second region. The first region includes a plurality of first planar active regions and a nonactive region. The nonactive region is located between or aside the plurality of first planar active regions and includes a second planar active region. The second region has a fin active region. The plurality of planar transistors are located in the plurality of first planar active regions within the first region. The fin-type field effect transistor is located on the fin active region within the second region. The first nonactive structure is located in the nonactive region between the plurality of planar transistors.

公开(公告)号：US20230326997A1

公开(公告)日：2023-10-12

申请号：US17746964

申请日：2022-05-18

Applicant: United Microelectronics Corp.

Inventor： Jia-He Lin ,  Yu-Ruei Chen ,  Yu-Hsiang Lin

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/0619 ,  H01L29/7851 ,  H01L29/66795

Abstract: A semiconductor device includes a substrate, a plurality of planar transistors, a fin-type field effect transistor and a first nonactive structure. The substrate includes a first region and a second region. The first region includes a plurality of first planar active regions and a nonactive region. The nonactive region is located between or aside the plurality of first planar active regions and includes a second planar active region. The second region has a fin active region. The plurality of planar transistors are located in the plurality of first planar active regions within the first region. The fin-type field effect transistor is located on the fin active region within the second region. The first nonactive structure is located in the nonactive region between the plurality of planar transistors.