公开(公告)号：US20210074843A1

公开(公告)日：2021-03-11

申请号：US16601364

申请日：2019-10-14

Applicant: United Microelectronics Corp.

Inventor： SHIN-HUNG LI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762

Abstract: A structure of a high voltage transistor includes a substrate. A gate insulating layer is disposed on the substrate. A shallow trench isolation structure is formed in the substrate adjacent to the gate insulating layer. The shallow trench isolation structure includes a first sidewall and a second sidewall. A top portion of the first sidewall merges with a side region of the gate insulating layer. A bottom surface of the shallow trench isolation structure is gradually decreasing in depth from the second sidewall to the first sidewall. A source/drain region is formed in the substrate at a side of the gate insulating layer and surrounding the shallow trench isolation structure.

公开(公告)号：US20190326398A1

公开(公告)日：2019-10-24

申请号：US16460813

申请日：2019-07-02

Applicant: United Microelectronics Corp.

Inventor： SHIN-HUNG LI ,  Kuan-Chuan Chen ,  Nien-Chung Li ,  Wen-Fang Lee ,  Chih-Chung Wang

IPC: H01L29/08 ,  H01L21/762 ,  H01L27/06 ,  H01L29/66 ,  H01L29/06

Abstract: Method for fabricating semiconductor device, including semiconductor layer having first device region and second device region. A shallow trench isolation (STI) structure is in the semiconductor layer and located at periphery of the first and second device regions. A first and second insulating layers are on the semiconductor layer and respectively located in the first and second device regions. A first gate structure is located on the first insulating layer. A source region and a drain region are in the semiconductor layer and are located at two sides of the first gate structure. A gate doped region is in a surface region of the semiconductor layer in the second device region to serve as a second gate structure. A channel layer is located on the second insulating layer. A source layer and a drain layer are on the STI structure and are located at two sides of the channel layer.