公开(公告)号：US10699958B2

公开(公告)日：2020-06-30

申请号：US16116730

申请日：2018-08-29

Applicant: United Microelectronics Corp.

Inventor： Wei-Chang Liu ,  Zhen Chen ,  Shen-De Wang ,  Wang Xiang ,  Wei Ta ,  Ling-Gang Fang ,  Shang Xue

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8239

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a first gate, a gate dielectric layer, a pair of second gates, a first spacer, and a second spacer. The first gate is disposed on a substrate. The gate dielectric layer is disposed between the first gate and the substrate. The pair of second gates are disposed on the substrate and respectively located at two sides of the first gate, wherein top surfaces of the pair of second gates are higher than a top surface of the first gate. The first spacer is disposed on sidewalls of the pair of second gates protruding from the top surface of the first gate and covers the top surface of the first gate. The second spacer is disposed between the gate dielectric layer and the pair of second gates, between the first gate and the pair of second gates, and between the first spacer and the pair of second gates.

公开(公告)号：US20200043791A1

公开(公告)日：2020-02-06

申请号：US16116730

申请日：2018-08-29

Applicant: United Microelectronics Corp.

Inventor： Wei-Chang Liu ,  Zhen Chen ,  Shen-De Wang ,  Wang Xiang ,  Wei Ta ,  Ling-Gang Fang ,  Shang Xue

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a first gate, a gate dielectric layer, a pair of second gates, a first spacer, and a second spacer. The first gate is disposed on a substrate. The gate dielectric layer is disposed between the first gate and the substrate. The pair of second gates are disposed on the substrate and respectively located at two sides of the first gate, wherein top surfaces of the pair of second gates are higher than a top surface of the first gate. The first spacer is disposed on sidewalls of the pair of second gates protruding from the top surface of the first gate and covers the top surface of the first gate. The second spacer is disposed between the gate dielectric layer and the pair of second gates, between the first gate and the pair of second gates, and between the first spacer and the pair of second gates.