公开(公告)号：US20230268437A1

公开(公告)日：2023-08-24

申请号：US17702831

申请日：2022-03-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chien Chang ,  Shen-De Wang ,  Cheng-Hua Yang ,  LINGGANG FANG ,  JIANJUN YANG ,  Wei Ta

IPC: H01L29/78 ,  H01L29/788 ,  H01L29/423 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/788 ,  H01L29/42328 ,  H01L27/088 ,  H01L29/66484 ,  H01L29/66825 ,  H01L29/66689 ,  H01L29/6656

Abstract: A power device includes a substrate, an ion well in the substrate, a body region in the ion well, a source doped region in the body region, a drain doped region in the ion well, and gates on the substrate between the source doped region and the drain doped region. The gates include a first gate adjacent to the source doped region, a second gate adjacent to the drain doped region, and a stacked gate structure between the first gate and the second gate.

公开(公告)号：US20230215946A1

公开(公告)日：2023-07-06

申请号：US18120995

申请日：2023-03-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Hua Yang ,  Chih-Chien Chang ,  Shen-De Wang

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/40 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L29/42368 ,  H01L29/402 ,  H01L29/1095

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, a first oxide layer, a field plate, and a second oxide layer. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure respectively. The first oxide layer includes a first portion disposed between the gate structure and the semiconductor substrate and a second portion disposed between the gate structure and the drain region. The field plate is partly disposed above the gate structure and partly disposed above the second portion of the first oxide layer. The second oxide layer includes a first portion disposed between the field plate and the gate structure and a second portion disposed between the field plate and the second portion of the first oxide layer.

公开(公告)号：US20210265376A1

公开(公告)日：2021-08-26

申请号：US16798126

申请日：2020-02-21

Applicant: United Microelectronics Corp.

Inventor： CHIA-CHING HSU ,  Wang Xiang ,  Shen-De Wang ,  Chun-Sung Huang

IPC: H01L27/11573 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/40 ,  H01L29/78 ,  H01L29/792 ,  H01L21/765 ,  H01L21/28 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, having cell region and high-voltage region. A memory cell is on the substrate within the cell region. The memory cell includes a memory gate structure and a selection gate structure on the substrate. A first spacer is sandwiched between or respectively on sidewalls of the memory cell structure and the selection gate structure. First high-voltage transistor is on the substrate within the high-voltage region. A first composite gate structure of the first high-voltage transistor includes a first gate structure on the substrate, an insulating layer with a predetermined thickness on the substrate in a -like structure or an L-like structure at cross-section, and a second gate structure on the insulating layer along the -like structure or the L-like structure. The selection gate structure and the second gate structure are originated from a same preliminary conductive layer.

公开(公告)号：US11011535B1

公开(公告)日：2021-05-18

申请号：US16724365

申请日：2019-12-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wang Xiang ,  Chia-Ching Hsu ,  Shen-De Wang ,  Weichang Liu

IPC: H01L27/11568 ,  H01L27/11573 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/28 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/027 ,  H01L29/78 ,  H01L29/51 ,  H01L21/311

Abstract: A method of integrating memory and metal-oxide-semiconductor (MOS) processes is provided, including steps of forming an oxide layer and a nitride layer on a substrate, forming a field oxide in a first area by an oxidation process with the nitride layer as a mask, wherein the oxidation process simultaneously forms a top oxide layer on the nitride layer, removing the top oxide layer, the nitride layer and the oxide layer in the first area, forming a polysilicon layer on the substrate, and patterning the polysilicon layer into MOS units in the first area and memory units in a second area.

公开(公告)号：US10192874B2

公开(公告)日：2019-01-29

申请号：US15626179

申请日：2017-06-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Chih-Chien Chang ,  Shen-De Wang

IPC: H01L29/788 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/66 ,  H01L29/423

Abstract: A nonvolatile memory cell includes a substrate having a drain region, a source region, and a channel region between the drain region and the source region. A floating gate and a select gate are disposed on the channel region. A control gate is disposed on the floating gate. An erase gate is disposed on the source region. The erase gate includes a lower end portion that extends into a major surface of the substrate.

公开(公告)号：US20170221913A1

公开(公告)日：2017-08-03

申请号：US15487419

申请日：2017-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu ,  Ko-Chi Chen ,  Shen-De Wang

IPC: H01L27/11529 ,  H01L27/11531

CPC classification number: H01L27/11529 ,  H01L27/11524 ,  H01L27/11531 ,  H01L27/11536 ,  H01L27/11539 ,  H01L27/11573

Abstract: A method of fabricating a semiconductor device includes providing a substrate with a memory region and a logic region, forming a recess of the substrate in the memory region, forming a non-volatile gate stack in the recess, and forming a logic gate stack in the logic region after forming the non-volatile gate stack.

公开(公告)号：US20170221911A1

公开(公告)日：2017-08-03

申请号：US15081946

申请日：2016-03-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Ko-Chi Chen ,  Shen-De Wang

IPC: H01L27/115 ,  G11C16/14 ,  H01L21/28 ,  G11C16/10 ,  H01L21/3205 ,  H01L29/66 ,  H01L29/423 ,  H01L29/788 ,  G11C16/04 ,  H01L21/311

CPC classification number: H01L29/40114 ,  G11C16/0408 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32055 ,  H01L27/11524 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

Abstract: The flash memory includes a stacked gate disposed on a substrate. The stacked gate includes an erase gate and two floating gates. Each floating gate has an acute angle pointing toward the erase gate. There is a high electric field formed around the acute angle so that the flash memory can perform an erase mode even at a lower operational voltage. Furthermore, the flash memory does not use any control gate to perform a write mode.

公开(公告)号：US09660106B2

公开(公告)日：2017-05-23

申请号：US14462550

申请日：2014-08-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Weichang Liu ,  Zhen Chen ,  Shen-De Wang ,  Wei Ta ,  Yi-Shan Chiu ,  Yuan-Hsiang Chang

IPC: H01L29/792 ,  H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L27/11573 ,  H01L21/311

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L21/31105 ,  H01L21/31144 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833

Abstract: A flash memory structure includes a memory gate on a substrate, a select gate adjacent to the memory gate, and an oxide-nitride spacer between the memory gate and the select gate, where the oxide-nitride spacer further includes an oxide layer and a nitride layer having an upper nitride portion and a lower nitride portion, and the upper nitride portion is thinner than the lower nitride portion.

公开(公告)号：US20160172200A1

公开(公告)日：2016-06-16

申请号：US14569794

申请日：2014-12-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： WEICHANG LIU ,  ZHEN CHEN ,  Shen-De Wang ,  Wei Ta ,  Yi-Shan Chiu ,  Yuan-Hsiang Chang ,  Chih-Chien Chang

IPC: H01L21/28

CPC classification number: H01L29/40117 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method for fabricating non-volatile memory device is disclosed. The method includes the steps of: providing a substrate having a stack structure thereon; performing a first oxidation process to form a first oxide layer on the substrate and the stack structure; etching the first oxide layer for forming a first spacer adjacent to the stack structure; performing a second oxidation process to form a second oxide layer on the substrate; forming a dielectric layer on the first spacer and the second oxide layer; and etching the dielectric layer for forming a second spacer.

Abstract translation: 公开了一种用于制造非易失性存储器件的方法。 该方法包括以下步骤：提供其上具有堆叠结构的衬底; 执行第一氧化工艺以在衬底和堆叠结构上形成第一氧化物层; 蚀刻用于形成邻近堆叠结构的第一间隔物的第一氧化物层; 执行第二氧化工艺以在所述衬底上形成第二氧化物层; 在所述第一间隔物和所述第二氧化物层上形成介电层; 并蚀刻用于形成第二间隔物的电介质层。

公开(公告)号：US08848454B2

公开(公告)日：2014-09-30

申请号：US13633732

申请日：2012-10-02

Applicant: United Microelectronics Corp.

Inventor： Feng-Ji Tsai ,  Shen-De Wang ,  Wen-Chung Chang ,  Ya-Huei Huang ,  Chien-Hung Chen

IPC: G11C11/34

CPC classification number: G11C16/0483 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/26 ,  H01L29/4234 ,  H01L29/42348 ,  H01L29/7923

Abstract: A method for programming a non-volatile memory cell is described. The memory cell includes a substrate, a gate over the substrate, a charge-trapping structure at least between the substrate and the gate, and first and second S/D regions in the substrate beside the gate. The method includes performing a channel-initiated secondary electron (CHISEL) injection process to inject electrons to the charge-trapping structure.

Abstract translation: 描述用于编程非易失性存储器单元的方法。 存储单元包括衬底，衬底上的栅极，至少在衬底和栅极之间的电荷捕获结构以及栅极旁边的衬底中的第一和第二S / D区域。 该方法包括执行通道引发的二次电子（CHISEL）注入过程以将电子注入电荷捕获结构。