公开(公告)号：US20140304572A1

公开(公告)日：2014-10-09

申请号：US13929758

申请日：2013-06-27

Applicant: University of Electronic Science and Technology of China

Inventor： Yajuan HE ,  Tingting XIA ,  Tao LUO ,  Wubing GAN ,  Bo ZHANG

IPC: G06F11/25

CPC classification number: G01R31/317 ,  G06F1/3243 ,  G06F1/3296 ,  G06F9/3869 ,  Y02D10/152 ,  Y02D10/172

Abstract: A pipelined processor including a combinational logic of several stages, a voltage regulator, a counter, a comparator, and a plurality of stage registers. Each stage register is disposed between two adjacent stages of the combinational logic. The stage register includes a flip-flop, a latch, an XOR gate, and a MUX module. When the high level of a register clock is coming, the flip-flop latches first data at the rising edge, and the latch receives second data during the high level. The data latched by the flip-flop and the latch respectively are compared by the XOR gate. If they are same, the output Error of the XOR gate is low level, and the output of the flip-flop is delivered to the next stage. Otherwise, the output Error of the XOR gate is high level, and the output of the latch is delivered to the next stage.

Abstract translation: 一种流水线处理器，包括几级的组合逻辑，电压调节器，计数器，比较器和多个级寄存器。 每个级寄存器被布置在组合逻辑的两个相邻级之间。 级寄存器包括触发器，锁存器，异或门和MUX模块。 当寄存器时钟的高电平到来时，触发器在上升沿锁存第一数据，并且锁存器在高电平期间接收第二数据。 由触发器和锁存器锁存的数据分别由XOR门进行比较。 如果它们相同，则XOR门的输出误差为低电平，触发器的输出被传送到下一级。 否则，异或门的输出误差为高电平，并将锁存器的输出传送到下一级。