公开(公告)号：US20170047908A1

公开(公告)日：2017-02-16

申请号：US14976363

申请日：2015-12-21

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Cheng-Chun Yeh

IPC: H03H11/28 ,  H01R24/28 ,  H01R31/06

CPC classification number: H03H11/28 ,  G06F13/4086 ,  Y02D10/14 ,  Y02D10/151

Abstract: A control circuit disposed in a connection line including a first power pin and a second power pin and including a native N-type transistor, a first impedance unit, and a second impedance unit is provided. The native N-type transistor includes a first gate, a first drain and a first source. The first drain is coupled to the first power pin. The first impedance unit is coupled between the first source and the second power pin. The second impedance unit is coupled between the first drain and the first gate. When the voltage level of the first power pin is equal to a pre-determined level, the first gate of the native N-type transistor receives an adjusting signal to adjust an equivalent impedance of the native N-type transistor.

Abstract translation: 设置在包括第一电源引脚和第二电源引脚并且包括天然N型晶体管，第一阻抗单元和第二阻抗单元的连接线中的控制电路。 天然N型晶体管包括第一栅极，第一漏极和第一源极。 第一漏极耦合到第一电源引脚。 第一阻抗单元耦合在第一电源和第二电源引脚之间。 第二阻抗单元耦合在第一漏极和第一栅极之间。 当第一电源引脚的电压电平等于预定电平时，本机N型晶体管的第一栅极接收调整信号以调节天然N型晶体管的等效阻抗。

公开(公告)号：US10211813B2

公开(公告)日：2019-02-19

申请号：US14976363

申请日：2015-12-21

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Cheng-Chun Yeh

IPC: G06F13/40 ,  H03H11/28

Abstract: A control circuit disposed in a connection line including a first power pin and a second power pin and including a native N-type transistor, a first impedance unit, and a second impedance unit is provided. The native N-type transistor includes a first gate, a first drain and a first source. The first drain is coupled to the first power pin. The first impedance unit is coupled between the first source and the second power pin. The second impedance unit is coupled between the first drain and the first gate. When the voltage level of the first power pin is equal to a pre-determined level, the first gate of the native N-type transistor receives an adjusting signal to adjust an equivalent impedance of the native N-type transistor.