公开(公告)号：US20130297962A1

公开(公告)日：2013-11-07

申请号：US13935860

申请日：2013-07-05

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Wen-Yu TSENG ,  Hsiao-Chyi LIN

IPC: G06F1/04

CPC classification number: G06F1/04 ,  G06F1/08

Abstract: A clock generator is provided. The clock generator includes a crystal oscillator, an inverter coupled to the crystal oscillator in parallel, a first circuit and a second circuit. The crystal oscillator has a first terminal and a second terminal The inverter generates a first signal and a second signal at the first and second terminals of the crystal oscillator, respectively. The first circuit coupled to the first terminal of the crystal oscillator generates a first clock signal with a constant frequency according to the first signal. The second circuit coupled to the second terminal of the crystal oscillator generates a second clock signal with a variable frequency according to the second signal.

Abstract translation: 提供时钟发生器。 时钟发生器包括晶体振荡器，并联耦合到晶体振荡器的反相器，第一电路和第二电路。 晶体振荡器具有第一端子和第二端子。逆变器分别在晶体振荡器的第一和第二端子处产生第一信号和第二信号。 耦合到晶体振荡器的第一端子的第一电路根据第一信号产生具有恒定频率的第一时钟信号。 耦合到晶体振荡器的第二端子的第二电路根据第二信号产生具有可变频率的第二时钟信号。

公开(公告)号：US20130304961A1

公开(公告)日：2013-11-14

申请号：US13889597

申请日：2013-05-08

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Hsiao-Chyi LIN ,  Wen-Yu TSENG

IPC: G06F13/40

CPC classification number: G06F13/409

Abstract: A HUB control chip implemented in a specific package is provided. The HUB control chip includes a plurality of transmission modules and a plurality of pins. The plurality of the pins include: a plurality of data pin groups coupled to one of the plurality of transmission modules respectively. Each of the plurality of data pin groups includes: a first sub-group, receiving and transmitting a first pair of differential signals conforming to the USB 2.0 standard; a second sub-group, receiving a second pair of differential signals conforming to the USB 3.0 standard; and a third sub-group, transmitting a third pair of differential signals conforming to the USB 3.0 standard. The number of the plurality of the pins is less than or equal to 52.

Abstract translation: 提供了在特定封装中实现的HUB控制芯片。 HUB控制芯片包括多个传输模块和多个引脚。 多个引脚包括：分别耦合到多个传输模块之一的多个数据引脚组。 多个数据引脚组中的每一个包括：第一子组，接收并发送符合USB 2.0标准的第一对差分信号; 第二子组，接收符合USB 3.0标准的第二对差分信号; 和第三子组，发送符合USB 3.0标准的第三对差分信号。 多个销的数量小于或等于52。