公开(公告)号：US20150349766A1

公开(公告)日：2015-12-03

申请号：US14607230

申请日：2015-01-28

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Quanfeng LIU ,  Huijie DUAN

IPC: H03K5/14 ,  H01L23/528 ,  H01L27/092

CPC classification number: H03K5/14 ,  H01L23/528 ,  H01L27/092

Abstract: A delay line circuit is provided and includes a fine delay unit and coarse delay units. Each fine delay circuit includes a first PMOS transistor; a first NMOS transistor; second PMOS transistors whose widths of gate features of the second PMOS transistor are equal; at least one third PMOS transistor, coupled between the power voltage and the source of the first PMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second PMOS transistors, second NMOS transistors whose widths of gate features of the second NMOS transistors are equal; and at least one third NMOS transistor, coupled between the ground voltage and the source of the first NMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second NMOS transistors.

Abstract translation: 提供延迟线路电路，并且包括精细延迟单元和粗略延迟单元。 每个精细延迟电路包括第一PMOS晶体管; 第一NMOS晶体管; 第二PMOS晶体管，其第二PMOS晶体管的栅极特征的宽度相等; 耦合在第一PMOS晶体管的电源电压和源极之间的至少一个第三PMOS晶体管，其栅极特征的宽度小于第二PMOS晶体管的栅极特征的宽度，第二NMOS晶体管的栅极特征的宽度 第二NMOS晶体管相等; 以及耦合在第一NMOS晶体管的接地电压和源极之间的至少一个第三NMOS晶体管，栅极特征的宽度小于第二NMOS晶体管的栅极特征的宽度。

公开(公告)号：US20150349765A1

公开(公告)日：2015-12-03

申请号：US14587628

申请日：2014-12-31

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Quanfeng LIU ,  Huijie DUAN

IPC: H03K5/14

CPC classification number: H03K5/14 ,  H01L23/528 ,  H01L27/092

Abstract: A delay line circuit is provided and includes a fine delay unit and coarse delay units. Each fine delay circuit includes a first PMOS transistor; a first NMOS transistor; second PMOS transistors whose widths of gate features of the second PMOS transistor are equal; at least one third PMOS transistor, coupled between the power voltage and the source of the first PMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second PMOS transistors, second NMOS transistors whose widths of gate features of the second NMOS transistors are equal; and at least one third NMOS transistor, coupled between the ground voltage and the source of the first NMOS transistor, whose width of gate features is smaller than the widths of the gate features of the second NMOS transistors.