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公开(公告)号：US20240250673A1
公开(公告)日：2024-07-25
申请号：US18419096
申请日：2024-01-22
IPC分类号： H03K5/14 , G01R31/317 , G06F1/08 , H03K5/00 , H03L7/081
CPC分类号： H03K5/14 , G01R31/31727 , G06F1/08 , H03L7/0812 , H03K2005/00058
摘要： A timing margin sensor includes a delay circuit to generate a calibrated delay that corresponds to a known delay value of a logic circuit. Circuitry locks a first delay produced by the delay circuit to a clock period of a clock signal that is associated with the known delay value. A programmable selector adjusts the first delay to generate the calibrated delay, the calibrated delay including a timing margin component. Circuitry detects a change in supply voltage provided to the logic circuit based on a detected change in the calibrated delay. Clock adjustment circuitry selectively changes the clock period based on the detected change in the calibrated delay.
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公开(公告)号：US12019573B2
公开(公告)日：2024-06-25
申请号：US18209083
申请日：2023-06-13
申请人： Uniquify, Inc.
发明人： Jung Lee , Venkat Iyer , Brett Murdock
IPC分类号： H03K5/14 , G06F13/16 , G06F13/362 , G06F13/42 , G11C8/18 , G11C29/02 , H03K5/133 , H03L7/08 , H03L7/081 , H03L7/10 , H03K5/00
CPC分类号： G06F13/3625 , G06F13/1689 , G06F13/4256 , G11C8/18 , G11C29/022 , G11C29/023 , G11C29/028 , H03K5/133 , H03K5/14 , H03L7/08 , H03L7/0812 , H03L7/10 , H03K2005/00019
摘要： A method for operating a data interface circuit whereby calibration adjustments for data bit capture are made without disturbing normal system operation includes initially establishing, using a first calibration method where a data bit pattern received by the data interface circuit is predictable, an optimal sampling point for sampling data bits received by the data interface circuit, and during a normal system operation and without disturbing the normal system operation, performing a second calibration method where the data bit pattern received by the data interface circuit is unpredictable. The second calibration method determines an amount of a timing drift for received data bit edge transitions and adjusts the optimal timing point determined by the first calibration method to create a revised optimal timing point. The second calibration method samples fringe timing points associated with the transition edges of a data bit.
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公开(公告)号：US20240120908A1
公开(公告)日：2024-04-11
申请号：US18378614
申请日：2023-10-10
发明人： Artur Langner , Colin Ramsay
CPC分类号： H03K5/14 , H03K5/19 , H03K2005/00084
摘要： An integrated circuit is described. This integrated circuit may include: a receive circuit, coupled to a segment of a LIN bus, that receives bits; a measurement circuit, coupled to the receive circuit, that measures: a rising-edge time and a falling-edge time in the bits, or a bit time and a second bit time in the bits; control logic, coupled to the measurement circuit, that compares the rising-edge time and the falling-edge time, or the bit time and the second bit time; a transmit circuit, coupled to the receive circuit, that transmits the bits on a second segment of the LIN bus; and a delay circuit, coupled to the control logic, that applies, based at least in part on the comparison, a delay to: one or more rising edges or falling edges in the bits; or one or more bit times or second bit times in the bits.
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公开(公告)号：US20240106425A1
公开(公告)日：2024-03-28
申请号：US18526226
申请日：2023-12-01
CPC分类号： H03K5/14 , H03K5/131 , H03K5/134 , H03K5/2481
摘要： A delay-locked loop (DLL) circuit includes a low pass filter coupled to a phase detector, and a digitally controlled delay line (DCDL) coupled to the low pass filter. The DCDL includes an input terminal, an output terminal coupled to an input terminal of the phase detector, and stages that propagate a signal along a first path from the input terminal to a selectable return stage and along a second path from the return stage to the output terminal. Each stage includes first and second inverters that selectively propagate the signal along the first and second paths, a third inverter that selectively propagates the signal from the first path to the second path, and either fourth and fifth inverters that selectively propagate the signal along the first and second paths, or a sixth inverter that selectively propagates the signal from the first path to the second path.
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公开(公告)号：US11855644B2
公开(公告)日：2023-12-26
申请号：US18155906
申请日：2023-01-18
CPC分类号： H03K5/14 , H03K5/131 , H03K5/134 , H03K5/2481
摘要： A digitally controlled delay line (DCDL) includes input and output terminals, and a plurality of stages that propagate a signal along a first signal path from the input terminal to a selectable return stage and along a second signal path from the return stage to the output terminal. Each stage includes a first inverter that selectively propagates the signal along the first signal path, a second inverter that selectively propagates the signal along the second signal path, and a third inverter that selectively propagates the signal from the first signal path to the second signal path. At least one of the first or third inverters includes a tuning portion including either a plurality of parallel, independently controllable p-type transistors coupled in series with a single independently controllable n-type transistor, or a plurality of parallel, independently controllable n-type transistors coupled in series with a single independently controllable p-type transistor.
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公开(公告)号：US20230412160A1
公开(公告)日：2023-12-21
申请号：US18326582
申请日：2023-05-31
发明人： David Vincenzoni
CPC分类号： H03K5/14 , H03K19/20 , H03L7/0812 , H03K2005/0015
摘要： In an embodiment, a circuit includes cascaded delay units arranged in a chain, each delay unit having an input-to-output delay time, wherein a first delay unit in the chain is configured to receive an input signal for propagating along the delay units in the chain, logic circuitry coupled to delay units in the chain, the logic circuitry configured to generate a clock signal as a logic combination of signals input to and output from the delay units in the chain and feedback circuitry configured to supply to the first delay unit in the chain a feedback signal, the feedback circuitry including a first feedback signal path from a last delay unit in the chain to the first delay unit in the chain and a second feedback signal path from an intermediate delay unit in the chain to the first delay unit in the chain, the intermediate delay unit arranged between the first delay unit in the chain and the last delay unit in the chain.
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7.发明公开公开(公告)号：US20230361804A1
公开(公告)日：2023-11-09
申请号：US18105815
申请日：2023-02-04
发明人： BYONGMO MOON , Taeryeong KIM , Seongook JUNG , Jeonghyeok YOU
CPC分类号： H04B1/40 , H03K19/20 , H03K3/037 , H03K5/14 , H03K5/2472 , H03K2005/00078
摘要： A transmitter circuit of an interface circuit includes a clock generating circuit, a pulse generating circuit, an overlapped multiplexing circuit, and an output circuit. The clock generating circuit generates a plurality of clocks having different phases. The pulse generating circuit generates a plurality of pulses based on the plurality of clocks. The overlapped multiplexing circuit receives a plurality of input signals in parallel, and sequentially outputs a plurality of overlapped signals based on the plurality of clocks, the plurality of input signals, and the plurality of pulses, and each overlapped signal includes bit values of two input signals among the plurality of input signals. The output circuit serially outputs bit values of the plurality of input signals in series based on the plurality of overlapped signal.
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公开(公告)号：US11742017B2
公开(公告)日：2023-08-29
申请号：US17700346
申请日：2022-03-21
发明人： Yasuo Satoh
IPC分类号： G11C11/4076 , H03L7/081 , H03K5/14 , H03K5/131 , H03K5/00
CPC分类号： G11C11/4076 , H03K5/131 , H03K5/14 , H03L7/0814 , H03L7/0818 , H03K2005/00019 , H03K2005/00241
摘要： Apparatuses and methods for adjusting a phase mixer circuit are disclosed. An example method includes providing data values stored by a plurality of first registers and a plurality of second registers. The method includes: during a first mode of operation, receiving the data values by groups of first registers of the plurality of the first registers and holding the data values by the plurality of second registers; during a second mode of operation, inverting a data value by one first register of the plurality of first registers at a time and holding the data values by the plurality of second registers; and during a third mode of operation, either inverting the data value by one first register of the plurality of first registers while holding the data values by the plurality of second registers or inverting a data value by one second register of the plurality of second registers while holding the data values by the plurality of first registers.
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公开(公告)号：US11693446B2
公开(公告)日：2023-07-04
申请号：US17506172
申请日：2021-10-20
摘要： On-chip spread spectrum synchronization between spread spectrum sources is provided. A spread spectrum amplitude of a signal of a spread spectrum reference clock is obtained using one or more delay lines of one or more delay elements in a skitter circuit. A spread width of the spread spectrum amplitude of the signal is determined, using one or more sticky latches in the skitter circuit, based on one or more edges of the signal. A delay line of the one or more delay elements corresponding to a falling edge of the spread width of the signal is identified using combinational circuitry of the skitter circuit. A spread spectrum signal of a spread spectrum slave clock is synchronized with the signal of the spread spectrum reference clock based on the delay line.
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公开(公告)号：US20230179193A1
公开(公告)日：2023-06-08
申请号：US17866517
申请日：2022-07-17
发明人： Tongsung Kim , Youngmin Jo , Chiweon Yoon , Byungkwan Chun , Byunghoon Jeong
CPC分类号： H03K5/14 , H03K5/135 , H03L7/0816 , H03K2005/00247
摘要： A memory package includes a plurality of memory chips, and an interface chip relaying communications between a controller and the plurality of memory chips and receiving a plurality of signals from the plurality of memory chips. The interface chip includes receivers outputting a data signal and a raw clock signal based on the plurality of signals, a delay circuit outputting a delay clock signal by applying an offset delay corresponding to ½ of one unit interval of the data signal and an additional delay to the raw clock signal, and a sampler sampling the data signal in synchronization with a clock signal. The delay circuit outputs the clock signal generated by removing the offset delay from the delay clock signal when the delay clock signal and the data signal have a phase difference corresponding to one unit interval of the data signal.
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