公开(公告)号：US20130205062A1

公开(公告)日：2013-08-08

申请号：US13753322

申请日：2013-01-29

Applicant: VMware, Inc.

Inventor： Qasim ALI ,  Raviprasad MUMMIDI ,  Vivek PANDEY ,  Kiran TATI

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F2212/151 ,  G06F2212/50 ,  G06F2212/651 ,  G06F2212/652

Abstract: The prioritization of large memory page mapping is a function of the access bits in the L1 page table. In a first phase of operation, the number of set access bits in each of the L1 page tables is counted periodically and a current count value is calculated therefrom. During the first phase, no pages are mapped large even if identified as such. After the first phase, the current count value is used to prioritize among potential large memory pages to determine which pages to map large. The system continues to calculate the current count value even after the first phase ends. When using hardware assist, the access bits in the nested page tables are used and when using software MMU, the access bits in the shadow page tables are used for large page prioritization.

Abstract translation: 大存储器页面映射的优先级是L1页表中的访问位的函数。 在第一操作阶段，周期性地对L1页表中的每一个中的设置访问比特数进行计数，并从其计算当前计数值。 在第一阶段，即使识别页面也不会映射大页面。 在第一阶段之后，当前的计数值用于在潜在的大内存页之间确定哪些页映射大。 即使在第一阶段结束之后，系统继续计算当前计数值。 当使用硬件辅助时，使用嵌套页表中的访问位，当使用软件MMU时，影子页表中的访问位用于大页面优先级。

公开(公告)号：US20140317375A1

公开(公告)日：2014-10-23

申请号：US14321174

申请日：2014-07-01

Applicant: VMware, Inc.

Inventor： Qasim ALI ,  Vivek PANDEY ,  Raviprasad MUMMIDI ,  Kiran TATI

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F2212/151 ,  G06F2212/50 ,  G06F2212/651 ,  G06F2212/652

Abstract: The prioritization of large memory page mapping is a function of the access bits in the L1 page table. In a first phase of operation, the number of set access bits in each of the L1 page tables is counted periodically and a current count value is calculated therefrom. During the first phase, no pages are mapped large even if identified as such. After the first phase, the current count value is used to prioritize among potential large memory pages to determine which pages to map large. The system continues to calculate the current count value even after the first phase ends. When using hardware assist, the access bits in the nested page tables are used and when using software MMU, the access bits in the shadow page tables are used for large page prioritization.

Abstract translation: 大存储器页面映射的优先级是L1页表中的访问位的函数。 在第一操作阶段，周期性地对L1页表中的每一个中的设置访问比特数进行计数，并从其计算当前计数值。 在第一阶段，即使识别页面也不会映射大页面。 在第一阶段之后，当前的计数值用于在潜在的大内存页之间确定哪些页映射大。 即使在第一阶段结束之后，系统继续计算当前计数值。 当使用硬件辅助时，使用嵌套页表中的访问位，当使用软件MMU时，影子页表中的访问位用于大页面优先级。

公开(公告)号：US20130138864A1

公开(公告)日：2013-05-30

申请号：US13747159

申请日：2013-01-22

Applicant: VMware, Inc,

Inventor： Qasim ALI ,  Raviprasad MUMMIDI ,  Kiran TATI

IPC: G06F12/08

CPC classification number: G06F12/08 ,  G06F9/455 ,  G06F11/3471 ,  G06F11/3485 ,  G06F12/1009 ,  G06F2201/815

Abstract: A system for identifying an exiting process and removing traces and shadow page table pages corresponding to the process' page table pages. An accessed minimum virtual address is maintained corresponding to an address space. In one embodiment, whenever a page table entry corresponding to the accessed minimum virtual address changes from present to not present, the process is determined to be exiting and removal of corresponding trace and shadow page table pages is begun. In a second embodiment, consecutive present to not-present PTE transitions are tracked for guest page tables on a per address space basis. When at least two guest page tables each has at least four consecutive present to not-present PTE transitions, a next present to not-present PTE transition event in the address space leads to the corresponding guest page table trace being dropped and the shadow page table page being removed.

Abstract translation: 用于识别退出处理并移除与进程页表页对应的跟踪和影子页表页的系统。 对应于地址空间维护访问的最小虚拟地址。 在一个实施例中，每当与所访问的最小虚拟地址相对应的页表条目从当前改变为不存在时，则确定该进程正在退出并且开始删除相应的跟踪和影子页表页。 在第二实施例中，针对每个地址空间的访客页表跟踪连续呈现到不存在的PTE转换。 当至少两个访客页表各自具有至少四个连续呈现到不存在的PTE转换时，地址空间中的下一个不存在的PTE转换事件将导致对应的客户页表跟踪被丢弃，并且阴影页表 被删除的页面