公开(公告)号：US20140360430A1

公开(公告)日：2014-12-11

申请号：US14297244

申请日：2014-06-05

Applicant: Veeco Instruments, Inc.

Inventor： Eric Armour ,  Sandeep Krishnan ,  Alex Zhang ,  Bojan Mitrovic ,  Alexander Gurary

IPC: C30B25/10 ,  C30B25/12

CPC classification number: C30B25/12 ,  C23C16/4584 ,  C23C16/4586 ,  C23C16/46 ,  C30B25/105 ,  Y10T29/49826

Abstract: A wafer carrier assembly for use in a system for growing epitaxial layers on one or more wafers by chemical vapor deposition (CVD), the wafer carrier assembly includes a wafer carrier body formed symmetrically about a central axis, and including a generally planar top surface that is situated perpendicularly to the central axis and a planar bottom surface that is parallel to the top surface. At least one wafer retention pocket is recessed in the wafer carrier body from the top surface. Each of the at least one wafer retention pocket includes a floor surface and a peripheral wall surface that surrounds the floor surface and defines a periphery of that wafer retention pocket. At least one thermal control feature includes an interior cavity or void formed in the wafer carrier body and is defined by interior surfaces of the wafer carrier body.

Abstract translation: 一种用于通过化学气相沉积（CVD）在一个或多个晶片上生长外延层的系统的晶片载体组件，晶片载体组件包括围绕中心轴线对称地形成的晶片载体主体，并且包括大致平坦的顶表面， 垂直于中心轴定位，平面底面平行于顶面。 至少一个晶片保留袋从顶表面凹陷在晶片载体主体中。 所述至少一个晶片保留袋中的每一个包括底板表面和围绕所述地板表面并限定所述晶片保持袋的周边的周壁表面。 至少一个热控制特征包括形成在晶片载体主体中并由晶片载体主体的内表面限定的内腔或空隙。

公开(公告)号：US20170121847A1

公开(公告)日：2017-05-04

申请号：US15403709

申请日：2017-01-11

Applicant: Veeco Instruments Inc.

Inventor： Eric Armour ,  Sandeep Krishnan ,  Alex Zhang ,  Bojan Mitrovic ,  Alexander Gurary

IPC: C30B25/12 ,  C23C16/46 ,  C23C16/458 ,  C30B25/10

CPC classification number: C30B25/12 ,  C23C16/4584 ,  C23C16/4586 ,  C23C16/46 ,  C30B25/105 ,  Y10T29/49826

Abstract: A wafer carrier assembly for use in a system for growing epitaxial layers on one or more wafers by chemical vapor deposition (CVD), the wafer carrier assembly includes a wafer carrier body formed symmetrically about a central axis, and including a generally planar top surface that is situated perpendicularly to the central axis and a planar bottom surface that is parallel to the top surface. At least one wafer retention pocket is recessed in the wafer carrier body from the top surface. Each of the at least one wafer retention pocket includes a floor surface and a peripheral wall surface that surrounds the floor surface and defines a periphery of that wafer retention pocket. At least one thermal control feature includes an interior cavity or void formed in the wafer carrier body and is defined by interior surfaces of the wafer carrier body.