公开(公告)号：US20170032974A1

公开(公告)日：2017-02-02

申请号：US14814153

申请日：2015-07-30

申请人： Veeco Instruments, Inc.

发明人： Eric Armour ,  George Papasouliotis ,  Daewon Kwon

IPC分类号： H01L21/324 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  C23C16/04 ,  H01L33/32 ,  H01L33/00 ,  C23C16/48 ,  C23C16/52 ,  C23C16/458 ,  H01L21/02 ,  H01L29/66

CPC分类号： H01L21/3245 ,  C23C16/047 ,  C23C16/301 ,  C23C16/4584 ,  C23C16/482 ,  C23C16/52 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66431 ,  H01L29/7787 ,  H01L33/0075 ,  H01L33/32

摘要： Embodiments include systems and methods for producing semiconductor wafers having reduced quantities of point defects. These systems and methods include a tunable ultraviolet (UV) light source, which is controlled to produce a raster of a UV light beam across a surface of a semiconductor wafer during epitaxial growth to dissociate point defects in the semiconductor wafer. In various embodiments, the tunable UV light source is configured external to a Metal Organic Chemical Vapor Deposition (MOCVD) chamber and controlled such that the UV light beam is directed though a window defined in a wall of the MOCVD chamber.

摘要翻译： 实施例包括用于制造具有减少量的点缺陷的半导体晶片的系统和方法。 这些系统和方法包括可调紫外（UV）光源，其被控制以在外延生长期间跨越半导体晶片的表面产生UV光束的光栅，以解离半导体晶片中的点缺陷。 在各种实施例中，可调谐UV光源被配置在金属有机化学气相沉积（MOCVD）室的外部，并被控制使得UV光束被引导通过限定在MOCVD室的壁中的窗口。

公开(公告)号：US09748113B2

公开(公告)日：2017-08-29

申请号：US14814153

申请日：2015-07-30

申请人： Veeco Instruments, Inc.

发明人： Eric Armour ,  George Papasouliotis ,  Daewon Kwon

IPC分类号： H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L21/324 ,  H01L29/20 ,  H01L29/66 ,  C23C16/48 ,  C23C16/52 ,  C23C16/458 ,  C23C16/04 ,  H01L29/205 ,  H01L29/778 ,  H01L33/32 ,  H01L33/00

CPC分类号： H01L21/3245 ,  C23C16/047 ,  C23C16/301 ,  C23C16/4584 ,  C23C16/482 ,  C23C16/52 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66431 ,  H01L29/7787 ,  H01L33/0075 ,  H01L33/32

摘要： Embodiments include systems and methods for producing semiconductor wafers having reduced quantities of point defects. These systems and methods include a tunable ultraviolet (UV) light source, which is controlled to produce a raster of a UV light beam across a surface of a semiconductor wafer during epitaxial growth to dissociate point defects in the semiconductor wafer. In various embodiments, the tunable UV light source is configured external to a Metal Organic Chemical Vapor Deposition (MOCVD) chamber and controlled such that the UV light beam is directed though a window defined in a wall of the MOCVD chamber.

公开(公告)号：US20240102166A1

公开(公告)日：2024-03-28

申请号：US18365629

申请日：2023-08-04

申请人： Veeco Instruments Inc.

发明人： Aniruddha Bagchi ,  Sandeep Krishnan ,  Eric Armour ,  Michael Chansky ,  Yuliy Rashkovsky ,  Andrew Hanser ,  Matthew Van Doren ,  William Wangard, III

IPC分类号： C23C16/458 ,  H01L21/687

CPC分类号： C23C16/4585 ,  H01L21/68771 ,  H01L21/68785

摘要： A wafer carrier includes a base including a generally planar bottom surface and a top surface that includes a plurality of platforms extending above the top surface. The wafer carrier includes a thermal cover defining a plurality of pockets. The thermal cover is configured to be coupled to the base by at least one fastener and the plurality of pockets are arranged such that each pocket of the plurality of pockets is aligned with a corresponding platform of the plurality of the platforms when the thermal cover is supported by a plurality of first pedestals that extend from the top surface of the base. A plurality of second pedestals are located along the plurality of platforms for supporting the one or more wafers, wherein each platform includes at least one second pedestal that extends from a top surface of the platform for supporting one wafer.

公开(公告)号：US20200063287A1

公开(公告)日：2020-02-27

申请号：US16107668

申请日：2018-08-21

申请人： Veeco Instruments Inc.

发明人： Bojan Mitrovic ,  Yuliy Rashkovsky ,  Eric Armour

IPC分类号： C30B25/12 ,  H01L21/677 ,  H01L21/687 ,  H01L21/02 ,  C30B25/16 ,  C30B25/10

摘要： A wafer carrier has a plurality of built-up pockets connected by raised interstitial spaces on a base. Top cover plates are affixed to the base by fasteners and separated from direct thermal contact b302y spacers.

公开(公告)号：US20200056284A1

公开(公告)日：2020-02-20

申请号：US15999697

申请日：2018-08-20

申请人： Veeco Instruments Inc.

发明人： Bojan Mitrovic ,  Yuliy Rashkovsky ,  Eric Armour

IPC分类号： C23C16/458 ,  H01L21/687

摘要： A wafer carrier has a plurality of built-up pockets connected by raised interstitial spaces on a base. Top cover plates are affixed to the base by fasteners and separated from direct thermal contact by spacers.

公开(公告)号：US20190157125A1

公开(公告)日：2019-05-23

申请号：US16191645

申请日：2018-11-15

申请人： Veeco Instruments Inc.

发明人： Alexander I. Gurary ,  Eric Armour

IPC分类号： H01L21/673 ,  H01L21/687 ,  C23C16/46 ,  C23C16/458

摘要： The invention relates generally to semiconductor fabrication technology and, more particularly, to chemical vapor deposition (CVD) processing and associated apparatus for addressing temperature non-uniformities on semiconductor wafer surfaces. Embodiments include a wafer carrier for use in a system for growing epitaxial layers on one or more wafers by CVD, the wafer carrier comprising a top plate and base plate which function coordinately to reduce temperature variability caused during CVD processing.

公开(公告)号：US10134617B2

公开(公告)日：2018-11-20

申请号：US14583346

申请日：2014-12-26

申请人： Veeco Instruments, Inc

发明人： Alexander I. Gurary ,  Eric Armour

IPC分类号： H01L21/673 ,  C23C16/458 ,  C23C16/46 ,  H01L21/687

摘要： The invention relates generally to semiconductor fabrication technology and, more particularly, to chemical vapor deposition (CVD) processing and associated apparatus for addressing temperature non-uniformities on semiconductor wafer surfaces. Embodiments include a wafer carrier for use in a system for growing epitaxial layers on one or more wafers by CVD, the wafer carrier comprising a top plate and base plate which function coordinately to reduce temperature variability caused during CVD processing.

公开(公告)号：US20170253967A1

公开(公告)日：2017-09-07

申请号：US15448019

申请日：2017-03-02

申请人： Veeco Instruments Inc.

发明人： Bojan Mitrovic ,  Eric Armour ,  Ian Kunsch

IPC分类号： C23C16/44 ,  H01L21/687 ,  H01L21/02 ,  C23C16/455 ,  C23C16/458

CPC分类号： C23C16/4401 ,  C23C16/45504 ,  C23C16/45519 ,  C23C16/4584 ,  C23C16/4588 ,  H01L21/02546 ,  H01L21/0262 ,  H01L21/68764 ,  H01L21/68771

摘要： An arrangement of two shutters radially outward from an injector block and a susceptor onto which a wafer carrier is removably mounted are configured to provide a flowpath through a reactor chamber that does not exhibit a vortex, thereby reducing or eliminating buildup on the inside of the reactor chamber and facilitating large temperature gradient between the injector block and the wafer carrier. This can be accomplished by introduction of a purge gas flow at a radially inner wall of an upper shutter, and in some embodiments the purge gas can have a different chemical composition than the precursor gas used to grow desired epitaxial structures on the wafer carrier.

公开(公告)号：US20170121847A1

公开(公告)日：2017-05-04

申请号：US15403709

申请日：2017-01-11

申请人： Veeco Instruments Inc.

发明人： Eric Armour ,  Sandeep Krishnan ,  Alex Zhang ,  Bojan Mitrovic ,  Alexander Gurary

IPC分类号： C30B25/12 ,  C23C16/46 ,  C23C16/458 ,  C30B25/10

CPC分类号： C30B25/12 ,  C23C16/4584 ,  C23C16/4586 ,  C23C16/46 ,  C30B25/105 ,  Y10T29/49826

摘要： A wafer carrier assembly for use in a system for growing epitaxial layers on one or more wafers by chemical vapor deposition (CVD), the wafer carrier assembly includes a wafer carrier body formed symmetrically about a central axis, and including a generally planar top surface that is situated perpendicularly to the central axis and a planar bottom surface that is parallel to the top surface. At least one wafer retention pocket is recessed in the wafer carrier body from the top surface. Each of the at least one wafer retention pocket includes a floor surface and a peripheral wall surface that surrounds the floor surface and defines a periphery of that wafer retention pocket. At least one thermal control feature includes an interior cavity or void formed in the wafer carrier body and is defined by interior surfaces of the wafer carrier body.

公开(公告)号：US20150187620A1

公开(公告)日：2015-07-02

申请号：US14583346

申请日：2014-12-26

申请人： Veeco Instruments Inc.

发明人： Alexander I. Gurary ,  Eric Armour

IPC分类号： H01L21/673 ,  C23C16/458

CPC分类号： H01L21/67333 ,  C23C16/4584 ,  C23C16/46 ,  H01L21/68735 ,  H01L21/68764 ,  H01L21/68771 ,  Y10T29/49826 ,  Y10T29/49837

摘要： The invention relates generally to semiconductor fabrication technology and, more particularly, to chemical vapor deposition (CVD) processing and associated apparatus for addressing temperature non-uniformities on semiconductor wafer surfaces. Embodiments include a wafer carrier for use in a system for growing epitaxial layers on one or more wafers by CVD, the wafer carrier comprising a top plate and base plate which function coordinately to reduce temperature variability caused during CVD processing.

摘要翻译： 本发明一般涉及半导体制造技术，更具体地说涉及用于解决半导体晶片表面温度不均匀性的化学气相沉积（CVD）处理和相关装置。 实施例包括用于通过CVD在一个或多个晶片上生长外延层的系统中的晶片载体，所述晶片载体包括顶板和底板，所述顶板和底板协调地起作用以降低在CVD处理期间引起的温度变化。