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公开(公告)号：US6119206A
公开(公告)日：2000-09-12
申请号：US680575
申请日：1996-07-12
CPC分类号： G06F11/3612
摘要： Stack tracebacks are performed in debugging and exception handling routines, and involve providing the values of non-volatile registers at the time of entry into each function in a call chain. One stack traceback technique includes performing the following two steps for each virtual address at which a function call in the call chain is made: (1) locating the tag section whose virtual address range includes the virtual address; and (2) locating a tag in the tag section found in step (1), whose virtual address range includes the virtual address. The tag found in step (2) indicates which of the values, if any, respectively held by the non-volatile registers upon entry to the particular function in which the above function call is made, are stored in a stack frame for the particular function at the time of the function call.
摘要翻译： 堆栈跟踪在调试和异常处理例程中执行，并且涉及在进入呼叫链中的每个功能时提供非易失性寄存器的值。 一种堆栈追溯技术包括对进行呼叫链中的功能调用的每个虚拟地址执行以下两个步骤：（1）定位虚拟地址范围包括虚拟地址的标签段; 以及（2）将标签定位在步骤（1）中找到的标签部分中，其虚拟地址范围包括虚拟地址。 在步骤（2）中找到的标签指示在进入上述功能调用的特定功能时分别由非易失性寄存器保持的值中的哪一个存储在特定功能的堆栈帧中 在函数调用时。
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2.发明授权Memory unit for connection to central processor unit and interconnecting bus 失效用于连接到中央处理器单元和互连总线的存储单元
公开(公告)号：US4016541A
公开(公告)日：1977-04-05
申请号：US461752
申请日：1974-04-17
CPC分类号： G06F13/18
摘要： In order to incorporate a very high speed memory subsystem into a computer system utilizing unified bus architecture, memory control apparatus associated with the very high speed memory is provided with a first port communicating directly with a system central processor and a second port interfacing with the unified bus. The memory control apparatus may include means for systematically refreshing volatile high speed memories. Multiple processor systems may be realized by taking advantage of the dual port characteristics of the very high speed memory subsystems associated with each central processor.
摘要翻译： 为了将非常高速的存储器子系统并入利用统一总线架构的计算机系统中，与非常高速存储器相关联的存储器控制装置具有与系统中央处理器直接通信的第一端口和与统一 总线。 存储器控制装置可以包括用于系统地刷新易失性高速存储器的装置。 可以通过利用与每个中央处理器相关联的非常高速存储器子系统的双端口特性来实现多处理器系统。
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