公开(公告)号：US07158727B2

公开(公告)日：2007-01-02

申请号：US10256821

申请日：2002-09-27

申请人： Vijay Kumar Pathak ,  Bharadwaj Parthasarathy ,  Srinath Devalapalli

发明人： Vijay Kumar Pathak ,  Bharadwaj Parthasarathy ,  Srinath Devalapalli

IPC分类号： H04B10/00

CPC分类号： H04J3/0685 ,  H03L7/18 ,  H04B10/29 ,  H04J2203/0089

摘要： The present invention provides a robust solution to the task of re-aligning data at the transmit end of a fiber optic or other high performance serial link, and also offers flexibility in the circuit board design approach. A high performance analog phase locked-loop circuit is used to simultaneously provide clock recovery for multiple bit streams. The power dissipation required to perform clock recovery is thereby reduced to a fraction of that required in conventional transmit systems. This analog phase locked loop produces plural phase output signals. An output multiplexer selects one phase for use in electrical to optical conversion.

摘要翻译： 本发明为在光纤或其他高性能串行链路的发射端重新对准数据的任务提供了可靠的解决方案，并且还提供了电路板设计方法的灵活性。 高性能模拟锁相环电路用于同时提供多个比特流的时钟恢复。 从而将执行时钟恢复所需的功耗降低到常规传输系统所需功率的一小部分。 该模拟锁相环产生多相输出信号。 输出多路复用器选择用于电光转换的一相。