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1.发明申请Interpolator based clock and data recovery (CDR) circuit with digitally programmable BW and tracking capability 有权基于Interpolator的时钟和数据恢复（CDR）电路，具有数字可编程的BW和跟踪功能公开(公告)号：US20050180536A1
公开(公告)日：2005-08-18
申请号：US10781099
申请日：2004-02-17
CPC分类号： H03L7/0814 , H04L7/0025 , H04L7/0337
摘要： The present invention facilitates clock and data recovery (330,716/718) for serial data streams (317,715) by providing a mechanism that can be employed to maintain a fixed tracking capability of an interpolator based CDR circuit (300,700) at multiple data rates (e.g., 800). The present invention further provides a wide data rate range CDR circuit (300,700), yet uses an interpolator design optimized for a fixed frequency. The invention employs a rate programmable divider circuit (606,656,706) that operates over a wide range of clock and data rates (e.g., 800) to provide various phase correction step sizes (e.g., 800) at a fixed VCO clock frequency. The divider (606,656,706) and a finite state machine (FSM) (612,662,712) of the exemplary CDR circuit (600,650,700) are manually programmed based on the data rate (614,667). Alternately, the data rate may be detected from a recovered serial data stream (718) during CDR operations (on-the-fly) utilizing a frequency detection circuit (725) to automatically program the divider (706) and FSM (712) to provide CDR circuit operation at the nearest base clock rate (716).
摘要翻译： 本发明通过提供一种机制来促进串行数据流（317,715）的时钟和数据恢复（330,716 / 718），该机制可用于以多个数据速率维持基于内插器的CDR电路（300,700）的固定跟踪能力（例如， 800）。 本发明还提供了宽数据速率范围CDR电路（300,700），但是使用针对固定频率优化的内插器设计。 本发明采用在宽范围的时钟和数据速率（例如800）上工作的速率可编程分频器电路（606,656,706），以在固定的VCO时钟频率下提供各种相位校正步长（例如800）。 基于数据速率（614,667）手动地对示例性CDR电路（600,650,700）的分频器（606,656,706）和有限状态机（FSM）（612,662,712）进行编程。 或者，可以在使用频率检测电路（725）的CDR操作（即时运行）期间从恢复的串行数据流（718）检测数据速率，以自动编程分频器（706）和FSM（712）以提供 CDR电路以最近的基准时钟速率（716）运行。
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公开(公告)号：US07158727B2
公开(公告)日：2007-01-02
申请号：US10256821
申请日：2002-09-27
IPC分类号： H04B10/00
CPC分类号： H04J3/0685 , H03L7/18 , H04B10/29 , H04J2203/0089
摘要： The present invention provides a robust solution to the task of re-aligning data at the transmit end of a fiber optic or other high performance serial link, and also offers flexibility in the circuit board design approach. A high performance analog phase locked-loop circuit is used to simultaneously provide clock recovery for multiple bit streams. The power dissipation required to perform clock recovery is thereby reduced to a fraction of that required in conventional transmit systems. This analog phase locked loop produces plural phase output signals. An output multiplexer selects one phase for use in electrical to optical conversion.
摘要翻译： 本发明为在光纤或其他高性能串行链路的发射端重新对准数据的任务提供了可靠的解决方案，并且还提供了电路板设计方法的灵活性。 高性能模拟锁相环电路用于同时提供多个比特流的时钟恢复。 从而将执行时钟恢复所需的功耗降低到常规传输系统所需功率的一小部分。 该模拟锁相环产生多相输出信号。 输出多路复用器选择用于电光转换的一相。
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公开(公告)号：US08977884B2
公开(公告)日：2015-03-10
申请号：US12964736
申请日：2010-12-09
IPC分类号： G06F1/00 , H03L7/06 , H03M9/00 , H04N5/12 , H04N21/43 , H04N21/4363 , H04N21/8547
CPC分类号： H04N5/126 , H04N21/4305 , H04N21/43635 , H04N21/8547
摘要： A bit stream includes playback data having an associated clock rate and a variable reference clock that is synchronized to the bit stream. A playback clock recovery signal and a data recovery signal are generated in response to the received reference clock. A playback clock frequency signal is generated in response to the playback clock recovery signal. A recovered playback clock is generated by using a divide by M divider, wherein the value of M used by the divide by M divider is determined in response to a programmable multiple of the clock rate associated with the playback information.
摘要翻译： 比特流包括具有相关联的时钟速率的重放数据和与比特流同步的可变参考时钟。 响应于接收的参考时钟产生重放时钟恢复信号和数据恢复信号。 响应于重放时钟恢复信号产生重放时钟频率信号。 通过使用M除法器进行除法来生成恢复的重放时钟，其中由与M分频器相除的M使用的值被响应于与重放信息相关联的时钟速率的可编程倍数来确定。
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公开(公告)号：US20120147266A1
公开(公告)日：2012-06-14
申请号：US12964736
申请日：2010-12-09
IPC分类号： H04N9/475
CPC分类号： H04N5/126 , H04N21/4305 , H04N21/43635 , H04N21/8547
摘要： A bit stream includes playback data having an associated clock rate and a variable reference clock that is synchronized to the bit stream. A playback clock recovery signal and a data recovery signal are generated in response to the received reference clock. A playback clock frequency signal is generated in response to the playback clock recovery signal. A recovered playback clock is generated by using a divide by M divider, wherein the value of M used by the divide by M divider is determined in response to a programmable multiple of the clock rate associated with the playback information.
摘要翻译： 比特流包括具有相关联的时钟速率的重放数据和与比特流同步的可变参考时钟。 响应于接收的参考时钟产生重放时钟恢复信号和数据恢复信号。 响应于重放时钟恢复信号产生重放时钟频率信号。 通过使用M除法器进行除法来生成恢复的重放时钟，其中由与M分频器相除的M使用的值被响应于与重放信息相关联的时钟速率的可编程倍数来确定。
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5.发明授权Interpolator based clock and data recovery (CDR) circuit with digitally programmable BW and tracking capability 有权基于Interpolator的时钟和数据恢复（CDR）电路，具有数字可编程的BW和跟踪功能公开(公告)号：US07315596B2
公开(公告)日：2008-01-01
申请号：US10781099
申请日：2004-02-17
IPC分类号： H04L7/00
CPC分类号： H03L7/0814 , H04L7/0025 , H04L7/0337
摘要： The present invention facilitates clock and data recovery (330,716/718) for serial data streams (317,715) by providing a mechanism that can be employed to maintain a fixed tracking capability of an interpolator based CDR circuit (300,700) at multiple data rates (e.g., 800). The present invention further provides a wide data rate range CDR circuit (300,700), yet uses an interpolator design optimized for a fixed frequency. The invention employs a rate programmable divider circuit (606,656,706) that operates over a wide range of clock and data rates (e.g., 800) to provide various phase correction step sizes (e.g., 800) at a fixed VCO clock frequency. The divider (606,656,706) and a finite state machine (FSM) (612,662,712) of the exemplary CDR circuit (600,650,700) are manually programmed based on the data rate (614,667). Alternately, the data rate may be detected from a recovered serial data stream (718) during CDR operations (on-the-fly) utilizing a frequency detection circuit (725) to automatically program the divider (706) and FSM (712) to provide CDR circuit operation at the nearest base clock rate (716).
摘要翻译： 本发明通过提供一种机制来促进串行数据流（317,715）的时钟和数据恢复（330,716 / 718），该机制可用于以多数据速率维持基于内插器的CDR电路（300,700）的固定跟踪能力（例如， 800）。 本发明还提供了宽数据速率范围CDR电路（300,700），但是使用针对固定频率优化的内插器设计。 本发明采用在宽范围的时钟和数据速率（例如800）上工作的速率可编程分频器电路（606,656,706），以在固定的VCO时钟频率下提供各种相位校正步长（例如800）。 基于数据速率（614,667）手动地对示例性CDR电路（600,650,700）的分频器（606,656,706）和有限状态机（FSM）（612,662,712）进行编程。 或者，可以在使用频率检测电路（725）的CDR操作（即时运行）期间从恢复的串行数据流（718）检测数据速率，以自动编程分频器（706）和FSM（712）以提供 CDR电路以最近的基准时钟速率（716）运行。
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公开(公告)号：US20060190888A1
公开(公告)日：2006-08-24
申请号：US11047204
申请日：2005-01-31
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5036
摘要： A system and method is disclosed for computer-assisted transistor design. A new transistor design can be generated based on characteristics of an existing transistor. The system for transistor design receives a first set of parameters for an existing transistor design that are functions of a first geometry that is descriptive of the existing transistor design. Next, the system establishes a set of constraints for the new transistor to be designed. The system then calculates pertinent dimensions of a geometry for the new transistor design based on the constraints and the first set of parameters.
摘要翻译： 公开了一种用于计算机辅助晶体管设计的系统和方法。 可以基于现有晶体管的特性生成新的晶体管设计。 用于晶体管设计的系统接收用于描述现有晶体管设计的第一几何形状的功能的现有晶体管设计的第一组参数。 接下来，系统为要设计的新晶体管建立一组约束。 然后，该系统基于约束和第一组参数来计算新晶体管设计的几何尺寸。
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