公开(公告)号：US07706431B2

公开(公告)日：2010-04-27

申请号：US11170876

申请日：2005-06-30

申请人： Ville Eerola ,  Samuli Pietilä ,  Harri Valio

发明人： Ville Eerola ,  Samuli Pietilä ,  Harri Valio

IPC分类号： H04B1/00

CPC分类号： G01S19/32 ,  G01S19/24 ,  G01S19/35 ,  H04B1/7085 ,  H04B2201/70701 ,  H04B2201/70715

摘要： A system architecture for a receiver to process multiple signals on a common carrier frequency from a satellite. The receiver is arranged such that the receiver receives input data transmitted from the satellite. A pilot signal is tracked from the input data using a correlation channel, and a data signal is tracked from the input data using a data code generator operatively connected to the correlation channel. In one embodiment of the invention, the data signal generator creates replica code for the data signal. In another embodiment of the invention, the system can switch between the data signal generator and pilot signal generator based upon the signal-to-noise ratio of the incoming signal.

摘要翻译： 一种用于接收机处理来自卫星的公共载波频率上的多个信号的系统架构。 接收机被布置成使得接收机接收从卫星发送的输入数据。 使用相关信道从输入数据跟踪导频信号，并且使用可操作地连接到相关信道的数据码发生器从输入数据跟踪数据信号。 在本发明的一个实施例中，数据信号发生器为数据信号产生复制代码。 在本发明的另一实施例中，系统可以基于输入信号的信噪比在数据信号发生器和导频信号发生器之间切换。

公开(公告)号：US20070009014A1

公开(公告)日：2007-01-11

申请号：US11170876

申请日：2005-06-30

申请人： Ville Eerola ,  Samuli Pietila ,  Harri Valio

发明人： Ville Eerola ,  Samuli Pietila ,  Harri Valio

IPC分类号： H04B1/00

CPC分类号： G01S19/32 ,  G01S19/24 ,  G01S19/35 ,  H04B1/7085 ,  H04B2201/70701 ,  H04B2201/70715

摘要： A system architecture for a receiver to process multiple signals on a common carrier frequency from a satellite. The receiver is arranged such that the receiver receives input data transmitted from the satellite. A pilot signal is tracked from the input data using a correlation channel, and a data signal is tracked from the input data using a data code generator operatively connected to the correlation channel. In one embodiment of the invention, the data signal generator creates replica code for the data signal. In another embodiment of the invention, the system can switch between the data signal generator and pilot signal generator based upon the signal-to-noise ratio of the incoming signal.

摘要翻译： 一种用于接收机处理来自卫星的公共载波频率上的多个信号的系统架构。 接收机被布置成使得接收机接收从卫星发送的输入数据。 使用相关信道从输入数据跟踪导频信号，并且使用可操作地连接到相关信道的数据码发生器从输入数据跟踪数据信号。 在本发明的一个实施例中，数据信号发生器为数据信号产生复制代码。 在本发明的另一实施例中，系统可以基于输入信号的信噪比在数据信号发生器和导频信号发生器之间切换。

公开(公告)号：US07505511B2

公开(公告)日：2009-03-17

申请号：US11317289

申请日：2005-12-23

申请人： Ville Eerola ,  Tapani Ritoniemi

发明人： Ville Eerola ,  Tapani Ritoniemi

IPC分类号： H04L27/30

CPC分类号： H04B1/7093

摘要： A matched filter for implementing the correlation of an input signal and a reference signal. The matched filter comprises N parallel M-sample long shift registers for receiving an equal number of input signals at the sampling frequency of the input signal, wherein N≧2, and then multiplexes one of the input signals and one of the reference signals at a time to calculation logic by applying alternately at least one combination of the input signals and the reference signals to the calculation logic. The calculation logic may then calculate the correlation time-dividedly for each combination of an input signal and a reference signal so that correlation results calculated from different signals appear at the output of the calculation means as a sequence.

摘要翻译： 用于实现输入信号和参考信号的相关性的匹配滤波器。 匹配滤波器包括N个并行M采样长移位寄存器，用于以输入信号的采样频率接收相等数量的输入信号，其中N≥2，然后将输入信号中的一个和参考信号中的一个复用在 通过将输入信号和参考信号的至少一个组合交替应用于计算逻辑来计算逻辑的时间。 然后，计算逻辑可以对输入信号和参考信号的每个组合分时地计算相关性，使得从不同信号计算的相关结果作为序列出现在计算装置的输出端。

公开(公告)号：US20080043822A1

公开(公告)日：2008-02-21

申请号：US11857329

申请日：2007-09-18

申请人： Ville Eerola ,  Tapani Ritoniemi

发明人： Ville Eerola ,  Tapani Ritoniemi

IPC分类号： H04B1/00

CPC分类号： H04B1/7085 ,  H04B1/7095

摘要： The present invention relates to a device for generating at least one code phase (Ce, Cp, Ci) the device comprising a shift register (702) comprising N outputs and to which a code sequence (Cin) to be phased is applied, and at least one logic branch (722, 723, 724) controlled by at least one combination control signal on the basis of which the logic branch combines the code phase from i outputs of the shift register (702). N is an integer greater than 2 and i is an integer between 2 and N. Said at least one logic branch preferably comprises i two-input selectors (901 to 909, 911 to 919, 921 to 929), to the first input of each of which is connected one input of the shift register (702) and to the second input is connected one combination control signal (ec0 to ec8, pc0 to pc8, lc0 to lc8), and an i-input combiner (910, 920, 930), to whose outputs are connected the outputs of said i selectors and from whose output said code phase is obtained.

摘要翻译： 本发明涉及一种用于产生至少一个码相（Ce，Cp，Ci）的装置，该装置包括包括N个输出的移位寄存器（702），并且应用要分阶段的码序列（Cin） 由至少一个组合控制信号控制的至少一个逻辑分支（722,723,724），基于该组合控制信号逻辑分支组合来自移位寄存器（702）的i个输出的代码相位。 N是大于2的整数，i是2和N之间的整数。所述至少一个逻辑分支优选地包括i个双输入选择器（901至909,911至919,921至929），每个 连接到移位寄存器（702）的一个输入端和第二输入端，将一个组合控制信号（ec 0〜ec 8，pc 0〜pc 8，lc 0〜lc 8）和i输入组合器 （910,920,930），其输出端连接所述i选择器的输出，并从其输出获得所述代码相位。

公开(公告)号：US20060209936A1

公开(公告)日：2006-09-21

申请号：US11317289

申请日：2005-12-23

申请人： Ville Eerola ,  Tapani Ritoniemi

发明人： Ville Eerola ,  Tapani Ritoniemi

IPC分类号： H04B1/00 ,  H04B1/707

CPC分类号： H04B1/7093

摘要： A matched filter for implementing the correlation of an input signal and a reference signal. The matched filter comprises N parallel M-sample long shift registers for receiving an equal number of input signals at the sampling frequency of the input signal, wherein N≧2, and then multiplexes one of the input signals and one of the reference signals at a time to calculation logic by applying alternately at least one combination of the input signals and the reference signals to the calculation logic. The calculation logic may then calculate the correlation time-dividedly for each combination of an input signal and a reference signal so that correlation results calculated from different signals appear at the output of the calculation means as a sequence.

摘要翻译： 用于实现输入信号和参考信号的相关性的匹配滤波器。 匹配滤波器包括N个并行M采样长移位寄存器，用于以输入信号的采样频率接收相等数量的输入信号，其中N≥2，然后将输入信号中的一个和参考信号中的一个复用在 通过将输入信号和参考信号的至少一个组合交替应用于计算逻辑来计算逻辑的时间。 然后，计算逻辑可以对输入信号和参考信号的每个组合分时地计算相关性，使得从不同信号计算的相关结果作为序列出现在计算装置的输出端。

公开(公告)号：US07852907B2

公开(公告)日：2010-12-14

申请号：US11645360

申请日：2006-12-21

申请人： Ville Eerola

发明人： Ville Eerola

IPC分类号： H04B1/00 ,  H04B1/06 ,  G01C21/00

CPC分类号： H04B1/709 ,  G01S19/30 ,  G01S19/37 ,  H04B2201/7071

摘要： A correlator (30) for performing a correlation with a received spread spectrum signal, comprising at least an input (30.1) for inputting samples of a received signal; at least one reference code input (30.2) for inputting at least one reference code, a correlator block comprising a data shift register (36) for receiving the signal samples; a number of register groups (31) comprising a code shift register (33) for receiving at least a part of at least one reference code; and a code register (34) for receiving data from the code shift register (33); configuration pathways (201, 202, 203) for arranging the connections between the code shift register and code register (33, 34) of the register groups (31) in a reconfigurable manner.

摘要翻译： 一种用于与接收的扩频信号进行相关的相关器（30），至少包括用于输入接收信号的采样的输入（30.1）; 用于输入至少一个参考码的至少一个参考码输入（30.2），包括用于接收信号样本的数据移位寄存器（36）的相关器块; 多个寄存器组（31），包括用于接收至少一个参考码的至少一部分的代码移位寄存器（33） 以及用于从代码移位寄存器（33）接收数据的代码寄存器（34）。 用于以可重新配置的方式布置寄存器组（31）的代码移位寄存器和代码寄存器（33,34）之间的连接的配置路径（201,202,203）。

公开(公告)号：US20070153882A1

公开(公告)日：2007-07-05

申请号：US11645360

申请日：2006-12-21

申请人： Ville Eerola

发明人： Ville Eerola

IPC分类号： H04B1/00

CPC分类号： H04B1/709 ,  G01S19/30 ,  G01S19/37 ,  H04B2201/7071

摘要： A correlator (30) for performing a correlation with a received spread spectrum signal, comprising at least an input (30.1) for inputting samples of a received signal; at least one reference code input (30.2) for inputting at least one reference code, a correlator block comprising a data shift register (36) for receiving the signal samples; a number of register groups (31) comprising a code shift register (33) for receiving at least a part of at least one reference code; and a code register (34) for receiving data from the code shift register (33); configuration pathways (201, 202, 203) for arranging the connections between the code shift register and code register (33, 34) of the register groups (31) in a reconfigurable manner.

摘要翻译： 一种用于与接收的扩频信号进行相关的相关器（30），至少包括用于输入接收信号的采样的输入（30.1）; 用于输入至少一个参考码的至少一个参考码输入（30.2），包括用于接收信号样本的数据移位寄存器（36）的相关器块; 多个寄存器组（31），包括用于接收至少一个参考码的至少一部分的代码移位寄存器（33） 以及用于从代码移位寄存器（33）接收数据的代码寄存器（34）。 用于以可重新配置的方式布置寄存器组（31）的代码移位寄存器和代码寄存器（33,34）之间的连接的配置路径（201,202,203）。

公开(公告)号：US07010024B1

公开(公告)日：2006-03-07

申请号：US09689854

申请日：2000-10-13

申请人： Ville Eerola ,  Tapani Ritoniemi

发明人： Ville Eerola ,  Tapani Ritoniemi

IPC分类号： H04B1/707

CPC分类号： H04B1/7093

摘要： A matched filter for implementing the correlation of an input signal and a reference signal. The matched filter comprises N parallel M-sample long shift registers for receiving an equal number of input signals at the sampling frequency of the input signal, wherein N2. The matched filter also stores K reference signals, wherein K2, and then multiplexes one of the input signals and one of the reference signals at a time to calculation logic by applying alternately at least one combination of the input signals and the reference signals to the calculation logic. The calculation logic may then calculate the correlation time-dividedly for each combination of an input signal and a reference signal so that correlation results calculated from different signals appear at the output of the calculation means as a sequence.

摘要翻译： 用于实现输入信号和参考信号的相关性的匹配滤波器。 匹配滤波器包括N个并行M采样长移位寄存器，用于以输入信号的采样频率接收相等数量的输入信号，其中N 2。 匹配滤波器还存储K个参考信号，其中K 2，然后一次将输入信号和参考信号中的一个多路复用到计算逻辑，交替地应用输入信号的至少一个组合 和参考信号给计算逻辑。 然后，计算逻辑可以对输入信号和参考信号的每个组合分时地计算相关性，使得从不同信号计算的相关结果作为序列出现在计算装置的输出端。

公开(公告)号：US06909739B1

公开(公告)日：2005-06-21

申请号：US09689750

申请日：2000-10-13

申请人： Ville Eerola ,  Tapani Ritoniemi

发明人： Ville Eerola ,  Tapani Ritoniemi

IPC分类号： H04B1/707 ,  H04B1/69

CPC分类号： H04B1/708 ,  H04B1/7093

摘要： A device for detecting a demodulated signal received by a spread spectrum receiver and converted into digital samples. The device is characterized by a matched filter for calculating the correlation between an incoming signal and at least one reference signal, an oscillator for generating a sampling frequency, and a sampling circuit for re-sampling the demodulated digital sample signal at the sampling frequency, which is such that the timing of samples of the references signals of the matched filter corresponds to the timing of a sample signal going from the sampling circuit to the matched filter. The device also includes a multiplier in which the sample signal is multiplied by a carrier replica generated locally before the sampling circuit or thereafter, to remove the carrier from the sample signal.

摘要翻译： 一种用于检测由扩频接收机接收并被转换为数字样本的解调信号的装置。 该装置的特征在于用于计算入射信号和至少一个参考信号之间的相关性的匹配滤波器，用于产生采样频率的振荡器和用于以采样频率重新采样解调数字采样信号的采样电路， 使得匹配滤波器的参考信号的采样的定时对应于从采样电路到匹配滤波器的采样信号的定时。 该装置还包括乘法器，其中采样信号乘以在采样电路之前本地生成的载波副本，此后，从采样信号中去除载波。

公开(公告)号：US06370556B1

公开(公告)日：2002-04-09

申请号：US08522362

申请日：1995-09-27

申请人： Tapio Saramäki ,  Tapani Ritoniemi ,  Ville Eerola ,  Timo Husu ,  Eero Pajarre ,  Seppo Ingalsuo

发明人： Tapio Saramäki ,  Tapani Ritoniemi ,  Ville Eerola ,  Timo Husu ,  Eero Pajarre ,  Seppo Ingalsuo

IPC分类号： G06F1716

CPC分类号： H03H17/0225 ,  H03H17/06

摘要： The invention relates to a method and an arrangement in a transposed digital FIR filter for multiplying a binary input signal by tap coefficients, and to a method for designing such a filter. The invention comprises a shift register (51, 52) shifting in the direction of the least significant bit and copying the most significant bit or filling in zero values. The register receives the binary input signal of the filter and has outputs for outputting the content of the desired bit positions. A plurality of bit-serial subtractor and adder elements (53-57) multiply the binary input signal by N+1 different tap coefficients by combining output bits of the shift register (51, 52). The subtractor and/or adder elements form a network wherein at least one element participates in the multiplying operation of at least two different tap coefficients.

摘要翻译： 本发明涉及一种用于将二进制输入信号与抽头系数相乘的转置数字FIR滤波器的方法和装置，以及一种用于设计这种滤波器的方法。 本发明包括移位寄存器（51,52），沿着最低有效位的方向移位，并复制最高有效位或填充零值。 寄存器接收滤波器的二进制输入信号，并具有用于输出所需位位置的内容的输出。 多个位串行减法器和加法器元件（53-57）通过组合移位寄存器（51,52）的输出位来将二进制输入信号乘以N + 1个不同抽头系数。 减法器和/或加法器元件形成网络，其中至少一个元件参与至少两个不同抽头系数的乘法运算。